AD7713ARZ-REEL Просмотр технического описания (PDF) - Analog Devices
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AD7713ARZ-REEL Datasheet PDF : 28 Pages
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AD7713
Parameter
A, S Versions1
Unit
Conditions/Comments
AIN3
Positive Full-Scale Calibration Limit13
Offset Calibration Limit15
Input Span
+(4.2 ϫ VREF)/GAIN V max
0 to VREF/GAIN
V max
+(3.2 ϫ VREF)/GAIN V min
+(4.2 ϫ VREF)/GAIN V max
GAIN Is the Selected PGA Gain
(Between 1 and 128).
GAIN Is the Selected PGA Gain
(Between 1 and 128).
GAIN Is the Selected PGA Gain
(Between 1 and 128).
GAIN Is the Selected PGA Gain
(Between 1 and 128).
POWER REQUIREMENTS
Power Supply Voltages
AVDD Voltage16
DVDD Voltage17
Power Supply Currents
AVDD Current
DVDD Current
Power Supply Rejection18
(AVDD and DVDD)19
Power Dissipation
Normal Mode
Standby (Power-Down) Mode
5 to 10
5
0.6
0.7
0.5
1
5.5
300
V nom
V nom
mA max
mA max
mA max
mA max
dB typ
mW max
µW max
± 5% for Specified Performance.
± 5% for Specified Performance.
AVDD = 5 V.
AVDD = 10 V.
fCLK IN = 1 MHz.
Digital Inputs 0 V to DVDD.
fCLK IN = 2 MHz.
Digital Inputs 0 V to DVDD.
Rejection w.r.t. AGND.
AVDD = DVDD = 5 V, fCLK IN = 1 MHz;
Typically 3.5 mW.
AVDD = DVDD = 5 V, Typically 150 µW.
NOTES
1Temperature range is: A Version, –40°C to +85°C; S Version, –55°C to +125°C.
2Applies after calibration at the temperature of interest.
3Positive full-scale error applies to both unipolar and bipolar input ranges.
4These errors will be of the order of the output noise of the part as shown in Table I after system calibration. These errors will be 20 µV typical after self-calibration
or background calibration.
5Recalibration at any temperature or use of the background calibration mode will remove these drift errors.
6These numbers are guaranteed by design and/or characterization.
7The AIN1 and AIN2 analog inputs present a very high impedance dynamic load that varies with clock frequency and input sample rate. The maximum recom-
mended source resistance depends on the selected gain.
8The analog input voltage range on the AIN1(+) and AIN2(+) inputs is given here with respect to the voltage on the AIN1(–) and AIN2(–) inputs. The input voltage
range on the AIN3 input is with respect to AGND. The absolute voltage on the AIN1 and AIN2 inputs should not go more positive than AV DD + 30 mV or more
negative than AGND – 30 mV.
9VREF = REF IN(+) – REF IN(–).
10 This common-mode voltage range is allowed, provided that the input voltage on AIN(+) and AIN(–) does not exceed AV DD + 30 mV and AGND – 30 mV.
11This error can be removed using the system calibration capabilities of the AD7713. This error is not removed by the AD7713’s self-calibration feature. The offset
drift on the AIN3 input is four times the value given in the Static Performance section of the specifications.
12Guaranteed by design, not production tested.
13After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, the device will
output all 0s.
14These calibration and span limits apply provided the absolute voltage on the AIN1 and AIN2 analog inputs does not exceed AV DD + 30 mV or go more negative than
AGND – 30 mV.
15The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.
16 Operating with AVDD voltages in the range 5.25 V to 10.5 V is guaranteed only over the 0°C to 70°C temperature range.
17 The ± 5% tolerance on the DVDD input is allowed provided that DVDD does not exceed AVDD by more than 0.3 V.
18Measured at dc and applies in the selected pass band. PSRR at 50 Hz will exceed 120 dB with filter notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz, or 50 Hz. PSRR at 60 Hz
will exceed 120 dB with filter notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz, or 60 Hz.
19PSRR depends on gain: gain of 1 = 70 dB typ; gain of 2 = 75 dB typ; gain of 4 = 80 dB typ; gains of 8 to 128 = 85 dB typ.
Specifications subject to change without notice.
–4–
REV. D
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