AD7713AR(RevC) Просмотр технического описания (PDF) - Analog Devices
Номер в каталоге
Компоненты Описание
производитель
AD7713AR Datasheet PDF : 28 Pages
| |||
AD7713
Parameter
REFERENCE INPUT
REF IN(+) – REF IN(–) Voltage
Input Sampling Rate, fS
Normal-Mode 50 Hz Rejection6
Normal-Mode 60 Hz Rejection6
Common-Mode Rejection (CMR)
Common-Mode 50 Hz Rejection6
Common-Mode 60 Hz Rejection6
Common-Mode Voltage Range10
DC Input Leakage Current @ +25°C
TMIN to TMAX
LOGIC INPUTS
Input Current
All Inputs Except MCLK IN
VINL, Input Low Voltage
VINH, Input High Voltage
MCLK IN Only
VINL, Input Low Voltage
VINH, Input High Voltage
LOGIC OUTPUTS
VOL, Output Low Voltage
VOH, Output High Voltage
Floating State Leakage Current
Floating State Output Capacitance12
TRANSDUCER BURN-OUT
Current
Initial Tolerance @ +25°C
Drift
RTD EXCITATION CURRENTS
(RTD1, RTD2)
Output Current
Initial Tolerance @ +25°C
Drift
Initial Matching @ +25°C
Drift Matching
Line Regulation (AVDD)
Load Regulation
A, S Versions1
+2.5 to AVDD/1.8
fCLK IN/512
100
100
100
150
150
AGND to AVDD
10
1
± 10
0.8
2.0
0.8
3.5
0.4
4.0
± 10
9
1
± 10
0.1
200
± 20
20
±1
3
200
200
Units
Conditions/Comments
V min to V max For Specified Performance. Part Is Functional with Lower
VREF Voltages
dB min
dB min
dB min
dB min
dB min
V min to V max
pA max
nA max
For Filter Notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz, 50 Hz, ±0.02 × f NOTCH
For Filter Notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz, 60 Hz, ±0.02 × f NOTCH
At DC
For Filter Notches of 2 Hz, 5 Hz, 10 Hz, 25 Hz, 50 Hz, ±0.02 × f NOTCH
For Filter Notches of 2 Hz, 6 Hz, 10 Hz, 30 Hz, 60 Hz, ±0.02 × f NOTCH
µA max
V max
V min
V max
V min
V max
V min
µA max
pF typ
ISINK = 1.6 mA
ISOURCE = 100 µA
µA nom
% typ
%/°C typ
µA nom
% max
ppm/°C typ
% max
ppm/°C typ
nA/V max
nA/V max
Matching Between RTD1 and RTD2 Currents
Matching Between RTD1 and RTD2 Current Drift
AVDD = +5 V
SYSTEM CALIBRATION
AIN1, AIN2
Positive Full-Scale Calibration Limit13
Negative Full-Scale Calibration Limit13
Offset Calibration Limit14, 15
Input Span14
AIN3
Positive Full-Scale Calibration Limit13
Offset Calibration Limit15
Input Span
+(1.05 × VREF)/GAIN
–(1.05 × VREF)/GAIN
–(1.05 × VREF)/GAIN
+0.8 × VREF/GAIN
+(2.1 × VREF)/GAIN
+(4.2 × VREF)/GAIN
0 to VREF/GAIN
+3.2 × VREF/GAIN
+(4.2 × VREF)/GAIN
V max
V max
V max
V min
V max
V max
V max
V min
V max
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
GAIN Is the Selected PGA Gain (Between 1 and 128)
NOTES
12Guaranteed by design, not production tested.
13After calibration, if the analog input exceeds positive full scale, the converter will output all 1s. If the analog input is less than negative full scale, then the device will
output all 0s.
14These calibration and span limits apply provided the absolute voltage on the AIN1 and AIN2 analog inputs does not exceed AV DD + 30 mV or go more negative
than AGND – 30 mV.
15The offset calibration limit applies to both the unipolar zero point and the bipolar zero point.
REV. C
–3–
Share Link: 