AD7721AN Просмотр технического описания (PDF) - Analog Devices

Номер в каталоге

Компоненты Описание

Список матч

AD7721AN

CMOS 16-Bit, 468.75 kHz, Sigma-Delta ADC

Analog Devices 

AD7721

Input Circuits

The purpose of antialiasing filters is to attenuate out of band

signals that would otherwise be mixed down into the signal

band. With traditional ADCs, high order filters using expensive

high tolerance passive components are often required to per-

form this function. Using oversampling, as employed on the

AD7721, this problem is considerably alleviated. Figure 4a

shows the digital filter frequency response. Due to the sampling

nature of the digital filter, the passband is repeated about the

operating clock frequency and at multiples of the clock fre-

quency. Out of band signals coincident with any of the filter

images are mixed down into the passband. Figure 4b shows the

frequency response of the antialias filter required to provide a

particular level of attenuation at the first image frequency. Fig-

ure 4c shows the frequency response of the antialias filter re-

quired to achieve the same level of attenuation with a traditional

ADC. The much smaller transition band can only be achieved

with a very high order filter.

0dB

fCLK

2fCLK

3fCLK

a. Digital Filter Frequency Response

OUTPUT DATA RATE

0dB

ANTIALIAS FILTER

RESPONSE

REQUIRED

ATTENUATION

fCLK

b. Frequency Response of Antialias Filter (AD7721)

The choice of the filter corner frequency will depend on the

amount of rolloff which is acceptable in-band and the attenua-

tion which is required at the first image frequency. For example,

when fCLK = 15 MHz, REXT = 50 Ω, CEXT = 7.84 nF, the in-

band rolloff is 1 dB and the attenuation at the first image fre-

quency is 31.1 dB. Increasing the size of the external resistor

above 50 Ω can cause increased distortion due to nonlinear

charging currents.

ANALOG

INPUT

REXT

REXT

CEXT

CEXT

VIN1

AD7721

VIN2

Figure 5. Simple RC Antialiasing Filter

Figure 6 shows a simple circuit that can be used to drive the

AD7721 in unipolar mode. The input of the AD7721 is sampled

by a 1.6 pF input capacitor. This creates glitches on the input

of the modulator. By placing the RC filter directly before the

AD7721, rather than before the operational amplifier, these

glitches are prevented from being fed back into the operational

amplifier and creating distortion. The resistor in this diagram,

as well as creating a pole for the antialias filter, also isolates the

storage capacitor from the operational amplifier which may

otherwise be unstable.

ANALOG

INPUT

COMMON

MODE

VOLTAGE

REXT

CEXT

VIN1

AD7721

VIN2

ANTIALIAS FILTER

RESPONSE

OUTPUT DATA RATE

0dB

REQUIRED

ATTENUATION

c. Frequency Response of Antialias Filter (Traditional ADC)

Figure 4. Frequency Response of Antialiasing Filters

Figure 5 shows a simple antialiasing filter which can be used

with the AD7721. The –3 dB corner frequency (f3 dB) of the

antialias filter is given by Equation 1, and the attenuation of the

filter is given by Equation 2. Attenuation at the first image

frequency is given by Equation 3.

f3 dB = 1/(2 π REXT CEXT)

Equation 1

( ) Attenuation = 20 log 1 /

1+

f / f 3 dB

2



Equation 2

Attenuation (First Image) =

( ) 20log 1/

1+

2

0.986 fCLK / f 3dB 

Equation 3

Figure 6. Antialiasing Circuits

A suitable operational amplifier is the AD847 if a ± 15 V power

supply is available. If only a +5 V power supply is available, the

AD820 can be used. This operational amplifier can be used with

input bandwidths up to 80 kHz. However, the slew rate of this

operational amplifier limits its performance to 80 kHz. Above

this frequency, the performance of the AD820 degrades.

For both filters, the capacitor CEXT should have a low tempera-

ture coefficient and should be linear to avoid distortion.

Polypropylene or polystyrene capacitors are suitable.

Offset and Gain Calibration

A calibration of offset and gain errors can be performed in both

serial and parallel modes by initiating a calibration cycle. During

this cycle, offset and gain registers in the filter are loaded with

values representing the dc offset of the analog modulator and a

modulator gain correction factor. In normal operation, the offset

register is subtracted from the digital filter output and this result

is then multiplied by the gain correction factor to obtain an

offset and gain corrected final result.

During the calibration cycle, in which the offset of the analog

modulator is evaluated, the inputs to the modulator are shorted

together internally. When the modulator and digital filter settle,

the average of 8 output results is calculated and stored in the

offset register. The gain of the modulator is determined by

REV. A

–9–

Share Link: