AD7013ARS Просмотр технического описания (PDF) - Analog Devices
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AD7013ARS Datasheet PDF : 20 Pages
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AD7013
RECEIVE SECTION TIMING (VAA = +5 V ± 10%; VDD = +5 V ± 10%; AGND = DGND =0 V, fMCLK = 6.2208 MHz;
TA = TMIN to TMAX, unless otherwise noted)
Parameter
t26
t27
t28
t29
t30
t31
t32
t33
t34
t35
t36
t37
Limit at TA =
–40°C to +85°C
10240t1
6144t1
30
85
4t1
2t1–20
2t1–20
–10
+10
64t1
4t1
–10
+10
12t1
128t1
2t1 + 20
2t1 + 20
Units
ns max
ns max
ns min
ns max
ns
ns min
ns min
ns min
ns max
ns
ns
ns min
ns max
ns min
ns max
ns max
ns max
Description
Power up Receive to RxCLK
CR13 = 0; Rx Offset Autocalibration On
CR13 = 1; Rx Offset autocalibration Off
Propagation Delay from MCLK Rising Edge to RxCLK Rising Edge
RxCLK Cycle Time; CR10 = 0; 2x Sampling of the Symbol Rate
RxCLK High Pulse Width; CR10 = 0
RxCLK Low Pulse Width; CR10 = 0
RxCLK Rising Edge to RxFRAME Rising Edge
RxCLK to RxFRAME Propagation Delay
RxFRAME Cycle Time; CR10 = 0
RxFRAME High Pulse Width; CR10 = 0
Propagation Delay from RxCLK Rising Edge to RxDATA Valid
DxCLK Rising Edge to Last Falling Edge of RxCLK
3-State to Receive Channel Valid
Receive Channel to 3-State Relinquish Time
1t37 is derived from the measured time taken by the receive channel outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured
number is then extrapolated back to remove the effects of charging or discharging the 80 pF capacitor. This means that the time quoted in the
Timing Characteristics is the true relinquish time of the part and as such is independent of external loading capacitance.
MCLK (I)
DxCLK (O)
CR14
RxCLK (O)
RxFRAME (O)
RxDATA (O)
The last DxCLK edge which is
used to write to Command Reg
One, setting CR14 to One
t26
t27
t31
t32
t34
1MSB
The last DxCLK edge which is
used to write to Command Reg
One, setting CR14 to Zero
t28
1LSB
t29
t30
t33
1
Q MSB
t35
Q LSB
0
15-BIT I WORD
NOTE: (O) INDICATES AN OUTPUT, (I) INDICATES AN INPUT
I/Q FLAG BIT
15-BIT I WORD
I/Q FLAG BIT
Figure 4. Receive Serial Interface Timing with 2 × Sampling of the Symbol Rate (CR10 = 0)
DxCLK (O)
CR18
RxCLK (O)
RxFRAME (O)
RxDATA (O)
The last DxCLK edge which is
used to write to Command Reg
One, setting CR14 to Zero
The last DxCLK edge which is
used to write to Command Reg
One, setting CR14 to One
t36
3- STATE
t37
ACTIVE
NOTE: (O) INDICATES AN OUTPUT, (I) INDICATES AN INPUT
3- STATE
Figure 5. Receive Serial Interface 3-State Timing
–8–
REV. A
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