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AD7013ARS

CMOS TIA IS-54 Baseband Receive Port

Analog Devices 

AD7013

RECEIVE SECTION TIMING (VAA = +5 V ± 10%; VDD = +5 V ± 10%; AGND = DGND = 0 V,fMCLK = 6.2208 MHz;

TA = TMIN to TMAX, unless otherwise noted)

Parameter

t16

t17

t18

t19

t20

t21

t22

t23

t24

t25

Limit at

TA = –40°C to +85°C

10240t1

6144t1

30

85

2t1

t1–20

t1–20

–10

10

32t1

2t1

–10

10

10t1

64t1

Units

ns max

ns max

ns min

ns max

ns

ns min

ns min

ns min

ns max

ns

ns

ns min

ns max

ns min

ns max

Description

Power-Up Receive to RxCLK

CR13 = 0, Rx Offset Autocalibration On

CR13 = 1, Rx Offset Autocalibration Off

Propagation Delay from MCLK Rising Edge to RxCLK Rising Edge

RxCLK Cycle Time; CR10 = 1; 4× Sampling of the Symbol Rate

RxCLK High Pulse Width; CR10 = 1

RxCLK Low Pulse Width; CR10 = 1

RxCLK Rising Edge to RxFRAME Rising Edge

RxFRAME Cycle Time; CR10 = 1

RxFRAME High Pulse Width; CR10 = 1

RxDATA Valid After RxCLK Rising Edge

DxCLK Rising Edge to Last Falling Edge RxCLK

MCLK (I)

DxCLK (O)

CR14

RxCLK (O)

RxFRAME (O)

RxDATA (O)

The last DxCLK edge which is

The last DxCLK edge which is

t25

used to write to Command Reg

used to write to Command Reg

One, setting CR14 to One

One, setting CR14 to Zero

t16

t21

t24

I MSB

t17

t22

I LSB 1 Q MSB

t18

t19

t20

t23

Q LSB 0 I MSB

I LSB 1 Q MSB

Q LSB 0

15-BIT

I WORD

I/Q

FLAG BIT

NOTE: (O) INDICATES AN OUTPUT, (I) INDICATES AN INPUT

15-BIT

Q WORD

I/Q

FLAG BIT

FINAL IQ PAIR PRIOR

TO POWER DOWN

Figure 3. Receive Serial Interface Timing with 4× Sampling of the Symbol Rate (CR10 = 1)

REV. A

–7–

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