AD7013ARS Просмотр технического описания (PDF) - Analog Devices

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AD7013ARS

CMOS TIA IS-54 Baseband Receive Port

Analog Devices 

AD7013

COMMAND REGISTER ONE

MSB

LSB

CR19 CR18 CR17 CR16 CR15 CR14 CR13 CR12 CR11 CR10

Rx SAMPLING VERNIER REGISTER

RESERVED

MSB

LSB

V3

V2

V1

V0

AUX DAC1

MSB

LSB

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

AUX DAC2

AUX DAC3 MSB

LSB

D7

D6

D5

D4

D3

D2

D1

D0

Figure 7. Internal AD7013 Registers

Table II. Command Register One

CR10 = 0

=1

CR11 = 0

=1

CR12 = 0

=1

CR13 = 0

=1

CR14 = 0

=1

CR15 = 0

=1

CR16 = 0

=1

CR17 = 0

=1

CR18 = 0

=1

CR19 = X

Low ADC sample rate. The sample rate of the receive ADCs are equal to 2× the symbol rate or equal to MCLK/128.

High ADC sample rate. The sample rate of the ADCs are equal to 4× the symbol rate or equal to MCLK/64.

RRC Receive FIR filter. This selects the root-raised consine filter response for the receive sigma-delta ADCs.

This is used to match the transmit RRC filter as required by the IS-54 standard. The frequency response is shown

in Figure 16.

Analog Mode FIR filter. This selects a filter response which has a sharper roll-off than the RRC FIR filter

and the frequency response has also been scaled to operate at a master clock frequency of 5.12 MHz. This allows

the sampling rate of the receive ADCs to be a multiple of 10 kHz as required for analog cellular. The frequency

response is shown in Figure 17.

Primary ADC inputs. This selects IRx and IRx as the I channel inputs and QRx and QRx as the

Q channel inputs.

Auxiliary ADC inputs. This selects AUX IRx and AUX IRx as the I channel inputs and AUX QRx and

AUX QRx as the Q channel inputs.

Auto ADC offset calibration. If auto calibration is selected, then an offset word for both ADCs is calculated

each time the receive ADCs are brought out of sleep mode. This allows ADC offsets within the AD7013 to be

automatically calibrated out.

User ADC offset calibration. When user calibration is selected, then contents of the offset registers are not updated

by the AD7013 when brought out of sleep mode. This allows the user to load the offset register externally thereby

allowing the AD7013 to also calibrate out external offsets.

Receive ADC sleep mode. This enters the I and Q ADCs into a low power sleep mode after outputting the current

IQ sample.

Receive ADC active mode. This activates the receive ADCs for normal operation.

8-Bit AUX DAC3 sleep mode. This enters the 8-bit auxiliary DAC into a low power sleep mode.

8-Bit AUX DAC3 active mode. This activates the 8-bit auxiliary DAC for normal operation.

8-Bit AUX DAC2 sleep mode. This enters the 8-bit auxiliary DAC into a low power sleep mode

8-Bit AUX DAC2 active mode. This activates the 8-bit auxiliary DAC for normal operation.

10-Bit AUX DAC1 sleep mode. This enters the 10-bit auxiliary DAC into a low power sleep mode.

10-Bit AUX DAC1 active mode. This activates the 10-bit auxiliary DAC for normal operation.

3-State Enable. This enables the 3-state buffers on the receive serial interface.

3-State Disable. This disables the 3-state buffers on the receive serial interface, entering the serial interface into

3-state.

No Action.

–10–

REV. A

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