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IDT723614L

CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2

Integrated Device Technology 

IDT723614 CMOS SyncBiFIFO™ WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

ALMOST EMPTY FLAGS (AEA, AEB)

The almost-empty flag of a FIFO is synchronized to the

port clock that reads data from its array. The state machine

that controls an almost-empty flag monitors a write-pointer

and a read-pointer comparator that indicates when the FIFO

SRAM status is almost empty, almost empty+1, or almost

empty+2. The almost-empty state is defined by the value of

the almost-full and almost-empty offset register (X). This

register is loaded with one of four preset values during a

device reset (see Reset above). An almost-empty flag is LOW

when the FIFO contains X or less long words in memory and

is HIGH when the FIFO contains (X+1) or more long words.

Two LOW-to-HIGH transitions of the almost-empty flag

synchronizing clock are required after a FIFO write for the

almost-empty flag to reflect the new level of fill. Therefore, the

almost-empty flag of a FIFO containing (X+1) or more long

words remains LOW if two cycles of the synchronizing clock

have not elapsed since the write that filled the memory to the

(X+1) level. An almost-empty flag is set HIGH by the second

LOW-to-HIGH transition of the synchronizing clock after the

FIFO write that fills memory to the (X+1) level. A LOW-to-

HIGH transition of an almost-empty flag synchronizing clock

begins the first synchronization cycle if it occurs at time tSKEW2

or greater after the write that fills the FIFO to (X+1) long words.

Otherwise, the subsequent synchronizing clock cycle can be

the first synchronization cycle (see Figure 17 and 18).

ALMOST FULL FLAGS (AFA, AFB)

The almost-full flag of a FIFO is synchronized to the port

clock that writes data to its array. The state machine that

controls an almost-full flag monitors a write-pointer and read-

pointer comparator that indicates when the FIFO SRAM

status is almost full, almost full-1, or almost full-2. The almost-

full state is defined by the value of the almost-full and almost-

empty offset register (X). This register is loaded with one of

four preset values during a device reset (see Reset above).

An almost-full flag is LOW when the FIFO contains (64-X) or

more long words in memory and is HIGH when the FIFO

contains [64-(X+1)] or less long words.

Two LOW-to-HIGH transitions of the almost-full flag

synchronizing clock are required after a FIFO read for the

almost-full flag to reflect the new level of fill. Therefore, the

almost-full flag of a FIFO containing [64-(X+1)] or less words

remains LOW if two cycles of the synchronizing clock have not

elapsed since the read that reduced the number of long words

in memory to [64-(X+1)]. An almost-full flag is set HIGH by the

second LOW-to-HIGH transition of the synchronizing clock

after the FIFO read that reduces the number of long words in

memory to [64-(X+1)]. A LOW-to-HIGH transition of an

almost-full flag synchronizing clock begins the first synchroni-

zation cycle if it occurs at time tSKEW2 or greater after the read

that reduces the number of long words in memory to [64-

(X+1)]. Otherwise, the subsequent synchronizing clock cycle

can be the first synchronization cycle (see Figure 19 and 20).

MAILBOX REGISTERS

Each FIFO has a 36-bit bypass register to pass command

and control information between port A and port B without

putting it in queue. The mailbox-select (MBA, MBB) inputs

choose between a mail register and a FIFO for a port data

transfer operation. A LOW-to-HIGH transition on CLKA writes

A0-A35 data to the mail1 register when a port A write is

selected by CSA, W/RA, and ENA with MBA HIGH. A LOW-

to-HIGH transition on CLKB writes B0-B35 data to the mail2

register when a port B write is selected by CSB, W/RB, and

ENB with both SIZ1 and SIZ0 HIGH. Writing data to a mail

register sets the corresponding flag (MBF1 or MBF2) LOW.

Attempted writes to a mail register are ignored while the mail

flag is LOW.

When the port A data outputs (A0-A35) are active, the

data on the bus comes from the FIFO2 output register when

MBA is LOW and from the mail2 register when MBA is HIGH.

When the port B data outputs (B0-B35) are active, the data on

the bus comes from the FIFO1 output register when either one

TABLE 4: FIFO1 FLAG OPERATION

Synchronized

Number of 36-Bit

to CLKB

Words in the FIFO1(1) EFB AEB

0

L

L

1 to X

H

L

(X+1) to [64-(X+1)]

H

H

(64-X) to 63

H

H

64

H

H

Synchronized

to CLKA

AFA FFA

H

H

H

H

H

H

L

H

L

L

TABLE 5: FIFO2 FLAG OPERATION

Synchronized

Number of 36-Bit

to CLKA

Words in the FIFO2(1) EFA AEA

0

L

L

1 to X

H

L

(X+1) to [64-(X+1)]

H

H

(64-X) to 63

H

H

64

H

H

Synchronized

to CLKB

AFB FFB

H

H

H

H

H

H

L

H

L

L

NOTE:

1. X is the value in the almost-empty flag and almost-full flag offset register.

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