IDT723614L30PF Просмотр технического описания (PDF) - Integrated Device Technology

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IDT723614L30PF

CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2

Integrated Device Technology 

IDT723614 CMOS SyncBiFIFO™ WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

chronous or coincident. The enables for each port are ar-

ranged to provide a simple bidirectional interface between

microprocessors and/or buses controlled by a synchronous

interface.

The full flag (FFA, FFB) and almost-full flag (AFA, AFB) of

a FIFO are two-stage synchronized to the port clock that

writes data to its array. The empty flag (EFA, EFB) and almost-

empty (AEA, AEB) flag of a FIFO are two stage synchronized

to the port clock that reads data from its array.

The IDT723614 is characterized for operation from 0°C to

70°C.

PIN CONFIGURATIONS (CONT.)

A23 1

A22 2

A21 3

GND 4

A20 5

A19 6

A18 7

A17 8

A16 9

A15 10

A14 11

A13 12

A12 13

A11 14

A10 15

GND 16

A9 17

A8 18

A7 19

VCC 20

A6 21

A5 22

A4 23

A3 24

GND 25

A2 26

A1 27

A0 28

EFA 29

AEA 30

90 B22

89 B21

88 GND

87 B20

86 B19

85 B18

84 B17

83 B16

82 B15

81 B14

80 B13

79 B12

78 B11

77 B10

76 GND

75 B9

74 B8

73 B7

72 VCC

71 B6

70 B5

69 B4

68 B3

67 GND

66 B2

65 B1

64 B0

63

62

61

EFB

AEB

AFB

TQFP (PN120-1, order code: PF)

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3146 drw 03

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