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IDT723614L20

CMOS SyncBiFIFO WITH BUS MATCHING AND BYTE SWAPPING 64 x 36 x 2

Integrated Device Technology 

IDT723614 CMOS SyncBiFIFO™ WITH BUS MATCHING AND BYTE SWAPPING

64 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

PORT-B MAIL REGISTER ACCESS

In addition to selecting port-B bus sizes for FIFO reads

and writes, the port B bus size select (SIZ0, SIZ1) inputs also

access the mail registers. When both SIZ0 and SIZ1 are

HIGH, the mail1 register is accessed for a port B long word

read and the mail2 register is accessed for a port B long word

write. The mail register is accessed immediately and any bus-

sizing operation that may be underway is unaffected by the

mail register access. After the mail register access is com-

plete, the previous FIFO access can resume in the next CLKB

cycle. The logic diagram in Figure 2 shows the previous bus-

size selection is preserved when the mail registers are ac-

cessed from port B. A port B bus size is implemented on each

rising CLKB edge according to the states of SIZ0_Q, SIZ1_Q,

and BE_Q.

BYTE SWAPPING

The byte-order arrangement of data read from FIFO1 or

data written to FIFO2 can be changed synchronous to the

rising edge of CLKB. Byte-order swapping is not available for

mail register data. Four modes of byte-order swapping (in-

cluding no swap) can be done with any data port size selec-

tion. The order of the bytes are rearranged within the long

word, but the bit order within the bytes remains constant.

Byte arrangement is chosen by the port B swap select

(SW0, SW1) inputs on a CLKB rising edge that reads a new

long word from FIFO1 or writes a new long word to FIFO2. The

byte order chosen on the first byte or first word of a new long

word read from FIFO1 or written to FIFO2 is maintained until

the entire long word is transferred, regardless of the SW0 and

SW1 states during subsequent writes or reads. Figure 3 is an

example of the byte-order swapping available for long words.

Performing a byte swap and bus size simultaneously for a

FIFO1 read first rearranges the bytes as shown in Figure 3,

then outputs the bytes as shown in Figure 1. Simultaneous

bus-sizing and byte-swapping operations for FIFO2 writes,

first loads the data according to Figure 1, then swaps the bytes

as shown in Figure 3 when the long word is loaded to FIFO2

RAM.

PARITY CHECKING

The port A inputs (A0-A35) and port B inputs (B0-B35)

each have four parity trees to check the parity of incoming (or

outgoing) data. A parity failure on one or more bytes of the port

A data bus is reported by a LOW level on the port parity error

flag (PEFA). A parity failure on one or more bytes of the port

B data input that are valid for the bus-size implementation is

reported by a LOW level on the port B parity error flag

(PEFB).Odd or even parity checking can be selected, and the

parity error flags can be ignored if this feature is not desired.

Parity status is checked on each input bus according to

the level of the odd/even parity (ODD/EVEN) select input. A

parity error on one or more valid bytes of a port is reported by

a LOW level on the corresponding port parity error flag (PEFA,

PEFB) output. Port A bytes are arranged as A0-A8, A9-A17,

CLKB

SIZ0

SIZ1

BE

G1 MUX

1

•

SIZ0 Q

••

1

D

Q

SIZ1 Q

• • BE Q

3146 drw fig 02

Figure 2. Logic Diagrams for SIZ0, SIZ1, and BE Register

14

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