IDT723614L15PQFGI(2009) Просмотр технического описания (PDF) - Integrated Device Technology

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IDT723614L15PQFGI
(Rev.:2009)

CMOS SyncBiFIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2

Integrated Device Technology 

IDT723614 CMOS SYNCBIFIFO™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

DC ELECTRICAL CHARACTERISTICS OVER RECOMMENDED RANGES OF

SUPPLY VOLTAGE AND OPERATING FREE-AIR TEMPERATURE

(Commercial: VCC = 5.0V ±10%, TA = 0°C to +70°C; Industrial; VCC = 5.0V ± 10%,TA = 40°C to +85°C)

Commercial

Com'l & Ind'l(1)

Symbol

Parameter

IDT723614L15

Min. Max.

IDT723614L20

Min. Max. Unit

fS

Clock Frequency, CLKA or CLKB

–

66.7

–

50

MHz

tCLK

Clock Cycle Time, CLKA or CLKB

15

–

20

–

ns

tCLKH Pulse Duration, CLKA and CLKB HIGH

6

–

8

–

ns

tCLKL Pulse Duration, CLKA and CLKB LOW

6

–

8

–

ns

tDS

Setup Time, A0-A35 before CLKA↑ and B0-B35 before CLKB↑

4

–

5

–

ns

tENS

Setup Time, CSA, W/RA, ENA and MBA before CLKA↑; CSB, W/RB and ENB

5

–

5

–

ns

before CLKB↑

tSZS

Setup Time, SIZ0, SIZ1, and BE before CLKB↑

4

–

5

–

ns

tSWS Setup Time, SW0 and SW1 before CLKB↑

5

–

7

–

ns

tPGS

Setup Time, ODD/EVEN and PGA before CLKA↑; ODD/EVEN and PGB before

4

–

5

–

ns

CLKB↑(2)

tRSTS Setup Time, RST LOW before CLKA↑ or CLKB↑(3)

5

–

6

–

ns

tFSS

Setup Time, FS0 and FS1 before RST HIGH

5

–

6

–

ns

tDH

Hold Time, A0-A35 after CLKA↑ and B0-B35 after CLKB↑

tENH

Hold Time, CSA, W/RA, ENA and MBA after CLKA↑; CSB, W/RB, and ENB

after CLKB↑

tSZH

Hold Time, SIZ0, SIZ1, and BE after CLKB↑

1

–

1

–

ns

1

–

1

–

ns

2

–

2

–

ns

tSWH

tPGH

tRSTH

tFSH

tSKEW1(4)

tSKEW2(4)

Hold Time, SW0 and SW1 after CLKB↑

Hold Time, ODD/EVEN and PGA after CLKA↑; ODD/EVEN and PGB after

CLKB↑(2)

Hold Time, RST LOW after CLKA↑ or CLKB↑(3)

Hold Time, FS0 and FS1 after RST HIGH

Skew Time, between CLKA↑ and CLKB↑ for EFA, EFB, FFA, and FFB

Skew Time, between CLKA↑ and CLKB↑ for AEA, AEB, AFA, and AFB

0

–

0

–

ns

0

–

0

–

ns

5

–

6

–

ns

4

–

4

–

ns

8

–

8

–

ns

14

–

16

–

ns

NOTES:

1. Industrial temperature range product for 20ns speed grade is available as a standard device. All other speed grades are available by special order.

2. Only applies for a clock edge that does a FIFO read.

3. Requirement to count the clock edge as one of at least four needed to reset a FIFO.

4. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.

8

JANUARY 14, 2009

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