IDT723614L15PFI(2002) Просмотр технического описания (PDF) - Integrated Device Technology

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IDT723614L15PFI
(Rev.:2002)

CMOS SyncBiFIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2

Integrated Device Technology 

IDT723614 CMOS SYNCBIFIFO™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

SIGNAL DESCRIPTIONS

RESET

The IDT723614 is reset by taking the Reset (RST) input LOW for at least

four port A clock (CLKA) and four port B clock (CLKB) LOW-to-HIGH

transitions. The Reset input can switch asynchronously to the clocks. A

device reset initializes the internal read and write pointers of each FIFO and

forces the Full Flags (FFA, FFB) LOW, the Empty Flags (EFA, EFB) LOW,

the Almost-Empty flags (AEA, AEB) LOW and the Almost-Full flags (AFA,

AFB) HIGH. A reset also forces the Mailbox Flags (MBF1, MBF2) HIGH.

After a reset, FFA is set HIGH after two LOW-to-HIGH transitions of CLKA

and FFB is set HIGH after two LOW-to-HIGH transitions of CLKB. The

device must be reset after power up before data is written to its memory.

A LOW-to-HIGH transition on the RST input loads the Almost-Full and

Almost-Empty Offset register (X) with the values selected by the Flag Select

(FS0, FS1) inputs. The values that can be loaded into the registers are

shown in Table 1.

FIFO WRITE/READ OPERATION

The state of port A data A0-A35 outputs is controlled by the port A Chip

Select (CSA) and the port A Write/Read select (W/RA). The A0-A35 outputs

are in the high-impedance state when either CSA or W/RA is HIGH. The A0-

A35 outputs are active when both CSA and W/RA are LOW. Data is loaded

into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH transition of CLKA

when CSA is LOW, W/RA is HIGH, ENA is HIGH, MBA is LOW, and FFA

is HIGH. Data is read from FIFO2 to the A0-A35 outputs by a LOW-to-HIGH

transition of CLKA when CSA is LOW, W/RA is LOW, ENA is HIGH, MBA

is LOW, and EFA is HIGH (see Table 2).

The port B control signals are identical to those of port A. The state of the

port B data (B0-B35) outputs is controlled by the port B Chip Select (CSB)

and the port B Write/Read select (W/RB). The B0-B35 outputs are in the high-

impedance state when either CSB or W/RB is HIGH. The B0-B35 outputs are

active when both CSB and W/RB are LOW. Data is loaded into FIFO2 from the

B0-B35 inputs on a LOW-to-HIGH transition of CLKB when CSB is LOW, W/RB

is HIGH, ENB is HIGH, EFB is HIGH, and either SIZ0 or SIZ1 is LOW. Data

is read from FIFO1 to the B0-B35 outputs by a LOW-to-HIGH transition of CLKB

when CSB is LOW, W/RB is LOW, ENB is HIGH, EFB is HIGH, and either SIZ0

or SIZ1 is LOW (see Table 3).

The setup and hold time constraints to the port clocks for the port Chip

Selects (CSA, CSB) and Write/Read selects (W/RA, W/RB) are only for

enabling write and read operations and are not related to high-impedance

control of the data outputs. If a port enable is LOW during a clock cycle, the

port Chip Select and Write/Read select can change states during the setup

and hold time window of the cycle.

SYNCHRONIZED FIFO FLAGS

Each FIFO is synchronized to its port clock through two flip-flop stages.

This is done to improve flag reliability by reducing the probability of

metastable events on the output when CLKA and CLKB operate asynchro-

nously to one another. EFA, AEA, FFA, and AFA are synchronized to CLKA.

EFB, AEB, FFB, and AFB are synchronized to CLKB. Tables 4 and 5 show

the relationship of each port flag to FIFO1 and FIFO2.

EMPTY FLAGS (EFA, EFB)

The Empty Flag of a FIFO is synchronized to the port clock that reads data

from its array. When the Empty Flag is HIGH, new data can be read to the FIFO

output register. When the Empty Flag is LOW, the FIFO is empty and attempted

FIFO reads are ignored. When reading FIFO1 with a byte or word size on port

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

B, EFB is set LOW when the fourth byte or second word of the last long word

is read.

The read pointer of a FIFO is incremented each time a new word is

clocked to the output register. The state machine that controls an Empty

Flag monitors a write-pointer and read-pointer comparator that indicates

when the FIFO SRAM status is empty, empty+1, or empty+2. A word written

to a FIFO can be read to the FIFO output register in a minimum of three

cycles of the Empty Flag synchronizing clock. Therefore, an Empty Flag is

LOW if a word in memory is the next data to be sent to the FIFO output

register and two cycles of the port clock that reads data from the FIFO have

not elapsed since the time the word was written. The Empty Flag of the FIFO

is set HIGH by the second LOW-to-HIGH transition of the synchronizing

clock, and the new data word can be read to the FIFO output register in the

following cycle.

A LOW-to-HIGH transition on an Empty Flag synchronizing clock begins

the first synchronization cycle of a write if the clock transition occurs at time tSKEW1

or greater after the write. Otherwise, the subsequent clock cycle can be the first

synchronization cycle (see Figure 14 and 15).

FULL FLAG (FFA, FFB)

The Full Flag of a FIFO is synchronized to the port clock that writes data

to its array. When the Full Flag is HIGH, a memory location is free in the

SRAM to receive new data. No memory locations are free when the full flag

is LOW and attempted writes to the FIFO are ignored.

Each time a word is written to a FIFO, the write pointer is incremented.

The state machine that controls a Full Flag monitors a write-pointer and

read-pointer comparator that indicates when the FIFO SRAM status is full,

full-1, or full-2. From the time a word is read from a FIFO, the previous

memory location is ready to be written in a minimum of three cycles of the

Full Flag synchronizing clock. Therefore, a Full Flag is LOW if less than two

cycles of the Full Flag synchronizing clock have elapsed since the next

memory write location has been read. The second LOW-to-HIGH transition

on the Full Flag synchronization clock after the read sets the Full Flag HIGH and

the data can be written in the following clock cycle.

A LOW-to-HIGH transition on a Full Flag synchronizing clock begins the

first synchronization cycle of a read if the clock transition occurs at time

tSKEW1 or greater after the read. Otherwise, the subsequent clock cycle can

be the first synchronization cycle (see Figure 16 and 17).

ALMOST-EMPTY FLAGS (AEA, AEB)

The Almost-Empty flag of a FIFO is synchronized to the port clock that

reads data from its array. The state machine that controls an Almost-Empty

flag monitors a write-pointer and a read-pointer comparator that indicates

when the FIFO SRAM status is almost-empty, almost-empty+1, or almost-

empty+2. The almost-empty state is defined by the value of the Almost-Full

and Almost-Empty Offset register (X). This register is loaded with one of

four preset values during a device reset (see Reset above). An Almost-

Empty flag is LOW when the FIFO contains X or less long words in memory

and is HIGH when the FIFO contains (X+1) or more long words.

Two LOW-to-HIGH transitions of the Almost-Empty flag synchronizing

clock are required after a FIFO write for the Almost-Empty flag to reflect the

new level of fill. Therefore, the Almost-Empty flag of a FIFO containing

(X+1) or more long words remains LOW if two cycles of the synchronizing

clock have not elapsed since the write that filled the memory to the (X+1)

level. An Almost-Empty flag is set HIGH by the second LOW-to-HIGH

transition of the synchronizing clock after the FIFO write that fills memory

to the (X+1) level. A LOW-to-HIGH transition of an Almost-Empty flag

synchronizing clock begins the first synchronization cycle if it occurs at time

10

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