IDT723614L20PF(2002) Просмотр технического описания (PDF) - Integrated Device Technology

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IDT723614L20PF
(Rev.:2002)

CMOS SyncBiFIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2

Integrated Device Technology 

IDT723614 CMOS SYNCBIFIFO™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

CLKB

FFB HIGH

CSB

W/RB

ENB

SW1, SW0

tSZS

BE

tSZS

SIZ1, SIZ0

(0, 1)

tSZH

tSZH

Little-

Endian

B0-B17

Big-

Endian

B18-B35

ODD/EVEN

PEFB

tENS

tENS

tENS

tSWS

tENH

tSWH

tSZS

tSZH

tSZS

tDS

tDS

(0, 1)

tSZH

tDH

tDH

tENH

tENS

tENH

NOT (1,1) (1)

tPPE

VALID

tPDPE

VALID

NOTES:

1. SIZ0 = HIGH and SIZ1 = HIGH writes data to the mail2 register.

2. PEFB indicates parity error for the following bytes: B35-B27 and B26-B18 for Big-Endian bus, and B17-B9 and B8-B0 for Little-Endian bus.

3146 drw08

DATA SWAP TABLE FOR WORD WRITES TO FIFO2

SWAP

MODE

SW1 SW0

L

L

L

H

H

L

H

H

WRITE

NO.

1

2

1

2

1

2

1

DATA WRITTEN TO FIFO2

BIG-ENDIAN

LITTLE-ENDIAN

B35-27

B26-18

B17-B9

B8-B0

A

B

C

D

C

D

A

B

D

C

B

A

B

A

D

C

C

D

A

B

A

B

C

D

B

A

D

C

DATA READ FROM FIFO2

A35-27

A

A26-A18

B

A17-A9

C

A8-A0

D

A

B

C

D

A

B

C

D

A

B

C

D

2

D

C

B

A

Figure 8. Port-B Word Write Cycle Timing for FIFO2

18

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