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IDT723614L20PQFI
(Rev.:2002)

CMOS SyncBiFIFO WITH BUS-MATCHING AND BYTE SWAPPING 64 x 36 x 2

Integrated Device Technology 

IDT723614 CMOS SYNCBIFIFO™ WITH BUS-MATCHING

AND BYTE SWAPPING 64 x 36 x 2

by a rising CLKB edge when a port B read is selected by CSB, W/RB, and ENB

with both SIZ1 and SIZ0 HIGH. The Mail2 Register Flag (MBF2) is set HIGH

by a LOW-to-HIGH transition on CLKA when port A read is selected by CSA,

W/RA, and ENA and MBA is HIGH. The data in the mail register remains intact

after it is read and changes only when new data is written to the register.

TABLE 4 — FIFO1 FLAG OPERATION

Number of 36-Bit

Words in the FIFO1(1)

0

1 to X

(X+1) to [64-(X+1)]

(64-X) to 63

64

Synchronized

to CLKB

EFB

AEB

L

L

H

L

H

H

H

H

H

H

Synchronized

to CLKA

AFA

FFA

H

H

H

H

H

H

L

H

L

L

TABLE 5 — FIFO2 FLAG OPERATION

Number of 36-Bit

Words in the FIFO2(1)

Synchronized

to CLKA

EFA

AEA

Synchronized

to CLKB

AFB

FFB

0

1 to X

(X+1) to [64-(X+1)]

(64-X) to 63

64

L

L

H

L

H

H

H

H

H

H

H

H

H

H

H

H

L

H

L

L

NOTE:

1. X is the value in the Almost-Empty flag and Almost-Full flag Offset register.

DYNAMIC BUS SIZING

The port B bus can be configured in a 36-bit long word, 18-bit word, or 9-

bit byte format for data read from FIFO1 or written to FIFO2. Word- and byte-

size bus selections can utilize the most significant bytes of the bus (Big-

Endian) or least significant bytes of the bus (Little-Endian). Port B bus size

can be changed dynamically and synchronous to CLKB to communicate

with peripherals of various bus widths.

The levels applied to the port B bus Size select (SIZ0, SIZ1) inputs and

the Big-Endian select (BE) input are stored on each CLKB LOW-to-HIGH

transition. The stored port B bus size selection is implemented by the next

rising edge on CLKB according to Figure 2.

Only 36-bit long-word data is written to or read from the two FIFO

memories on the IDT723614. Bus-matching operations are done after data

is read from the FIFO1 RAM and before data is written to the FIFO2 RAM.

Port B bus sizing does not apply to mail register operations.

BUS-MATCHING FIFO1 READS

Data is read from the FIFO1 RAM in 36-bit long word increments. If a long

word bus size is implemented, the entire long word immediately shifts to the

FIFO1 output register. If byte or word size is implemented on port B, only

the first one or two bytes appear on the selected portion of the FIFO1 output

register, with the rest of the long word stored in auxiliary registers. In this case,

COMMERCIAL AND INDUSTRIAL

TEMPERATURE RANGES

subsequent FIFO1 reads with the same bus-size implementation output the rest

of the long word to the FIFO1 output register in the order shown by Figure 2.

Each FIFO1 read with a new bus-size implementation automatically unloads

data from the FIFO1 RAM to its output register and auxiliary registers. Therefore,

implementing a new port B bus size and performing a FIFO1 read before all bytes

or words stored in the auxiliary registers have been read results in a loss of the

unread long word data.

When reading data from FIFO1 in byte or word format, the unused B0-

B35 outputs remain inactive but static, with the unused FIFO1 output

register bits holding the last data value to decrease power consumption.

BUS-MATCHING FIFO2 WRITES

Data is written to the FIFO2 RAM in 36-bit long word increments. FIFO2

writes, with a long-word bus size, immediately store each long word in

FIFO2 RAM. Data written to FIFO2 with a byte or word bus size stores the

initial bytes or words in auxiliary registers. The CLKB rising edge that writes

the fourth byte or the second word of long word to FIFO2 also stores the

entire long word in FIFO2 RAM. The bytes are arranged in the manner

shown in Figure 2.

Each FIFO2 write with a new bus-size implementation resets the state

machine that controls the data flow from the auxiliary registers to the FIFO2

RAM. Therefore, implementing a new bus size and performing a FIFO2

write before bytes or words stored in the auxiliary registers have been

loaded to FIFO2 RAM results in a loss of data.

PORT-B MAIL REGISTER ACCESS

In addition to selecting port-B bus sizes for FIFO reads and writes, the

port B bus Size select (SIZ0, SIZ1) inputs also access the mail registers.

When both SIZ0 and SIZ1 are HIGH, the mail1 register is accessed for a port

B long word read and the mail2 register is accessed for a port B long word

write. The mail register is accessed immediately and any bus-sizing

operation that may be underway is unaffected by the mail register access.

After the mail register access is complete, the previous FIFO access can

resume in the next CLKB cycle. The logic diagram in Figure 3 shows the

previous bus-size selection is preserved when the mail registers are

accessed from port B. A port B bus size is implemented on each rising CLKB

edge according to the states of SIZ0_Q, SIZ1_Q, and BE_Q.

BYTE SWAPPING

The byte-order arrangement of data read from FIFO1 or data written to

FIFO2 can be changed synchronous to the rising edge of CLKB. Byte-order

swapping is not available for mail register data. Four modes of byte-order

swapping (including no swap) can be done with any data port size selection.

The order of the bytes are rearranged within the long word, but the bit order

within the bytes remains constant.

Byte arrangement is chosen by the port B Swap select (SW0, SW1)

inputs on a CLKB rising edge that reads a new long word from FIFO1 or

writes a new long word to FIFO2. The byte order chosen on the first byte or

first word of a new long word read from FIFO1 or written to FIFO2 is

maintained until the entire long word is transferred, regardless of the SW0

and SW1 states during subsequent writes or reads. Figure 4 is an example

of the byte-order swapping available for long words. Performing a byte swap

and bus size simultaneously for a FIFO1 read first rearranges the bytes as

shown in Figure 4, then outputs the bytes as shown in Figure 2. Simulta-

neous bus-sizing and byte-swapping operations for FIFO2 writes, first loads

the data according to Figure 2, then swaps the bytes as shown in Figure 4 when

the long word is loaded to FIFO2 RAM.

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