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IDT723622

CMOS SyncBiFIFO 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2

Integrated Device Technology 

IDT723622/723632/723642 CMOS SyncBiFIFO™

256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTIONS (CONT.)

Symbol

MBB

MBF1

MBF2

ORA

ORB

RST1

RST2

W/RA

W/RB

Name

Port-B Mailbox

Select

Mail1 Register

Flag

Mail2 Register

Flag

Output-Ready

Flag

Output-Ready

Flag

FIFO1 Reset

FIFO2 Reset

Port-A Write/

Read Select

Port-B Write/

Read Select

I/O

I

O

O

O

(Port A)

O

(Port B)

I

I

I

I

Description

A HIGH level on MBB chooses a mailbox register for a port-B read or

write operation. When the B0-B35 outputs are active, a HIGH level on

MBB selects data from the mail1 register or output and a LOW level selects

FIFO1 output-register data for output.

MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data

to the mail1 register. Writes to the mail1 register are inhibited while MBF1 is

LOW. MBF1 is set HIGH by a LOW-to-HIGH transition of CLKB when a port-B

read is selected and MBB is HIGH. MBF1 is set HIGH when FIFO1 is reset.

MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the

mail2 register. Writes to the mail2 register are inhibited while MBF2 is LOW.

MBF2 is set HIGH by a LOW-to-HIGH transition of CLKA when a port-A read is

selected and MBA is HIGH. MBF2 is also set HIGH when FIFO2 is reset.

ORA is synchronized to the LOW-to-HIGH transition of CLKA. When ORA is

LOW, FIFO2 is empty and reads from its memory are disabled. Ready data

is present on the output register of FIFO2 when ORA is HIGH. ORA is

forced LOW when FlFO2 is reset and goes HIGH on the third LOW-to-HIGH

transition of CLKA after a word is loaded to empty memory.

ORB is synchronized to the LOW-to-HIGH transition of CLKB. When ORB

is LOW, FlFO1 is empty and reads from its memory are disabled. Ready data

is present on the output register of FIFO1 when ORB is HIGH. ORB is forced LOW

when FIFO1 is reset and goes HIGH on the third LOW-to-HIGH transition of CLKB

after a word is loaded to empty memory.

To reset FIFO1, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH

transitions of CLKB must occur while RST1 is LOW. The LOW-to-HIGH transition

of RST1 latches the status of FSO and FS1 for AFA and AEB offset selection.

FIFO1 must be reset upon power up before data is written to its RAM.

To reset FIFO2, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH

transitions of CLKB must occur while RST2 is LOW. The LOW-to-HIGH transition

of RST2 latches the status of FSO and FS1 for AFB and AEA offset selection.

FIFO2 must be reset upon power up before data is written to its RAM.

A HIGH selects a write operation and a LOW selects a read operation on port A

for a LOW-to-HIGH transition of CLKA. The AO-A35 outputs are in

the HIGH impedance state when W/RA is HIGH.

A LOW selects a write operation and a HIGH selects a read operation on port B

for a LOW-to-HIGH transition of CLKB. The BO-B35 outputs are in the HIGH

impedance state when W/RB is LOW.

5.22

5

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