723622L15 Просмотр технического описания (PDF) - Integrated Device Technology

Номер в каталоге

Компоненты Описание

Список матч

723622L15

CMOS SyncBiFIFO 256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2

Integrated Device Technology 

IDT723622/723632/723642 CMOS SyncBiFIFO™

256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

CLKB

CSB

W/RB

MBB

ENB

LOW

LOW

tENS

tENS

tENH

tENH

tCLKH

tCLK

tCLKL

IRB

HIGH

tDS

tDH

B0 - B35

CLKA

W1

(1)

tSKEW1

tCLK

tCLKH tCLKL

1

2

ORA

CSA

LOW

Old Data in FIFO2 Output Register

3

tPOR

tPOR

W/RA LOW

MBA LOW

tENS

tENH

ENA

tA

A0 -A35

Old Data in FIFO2 Output Register

W1

3022 drw 11

NOTE:

1. tSKEW1 is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output

register in three CLKA cycles. If the time between the rising CLKB edge and rising CLKA edge is less than tSKEW1, then the transition of ORA HIGH and

load of the first word to the output register may occur one CLKA cycle later than shown.

Figure 8. ORA Flag Timing and First Data Word Fallthrough when FIFO2 is Empty.

5.22

18

Share Link: