IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
CLKA
tCLKH
tCLK
tCLKL
COMMERCIAL TEMPERATURE RANGE
IRA
CSA
W/RA
MBA
ENA
A0 - A35
NOTE:
1. Written to FIFO1.
tENS
tENS
tENH
tENH
tENS
tENH
tENS
tENH
tDS
tDH
W1(1)
tENS
tENH
W2(1)
tENS
tENH
No Operation
Figure 3. Port-A Write Cycle Timing for FIFO1
3022 drw 06
CLKB
IRB
CSB
W/RB
MBB
ENB
B0 - B35
tCLKH
tCLK
tCLKL
tENS
tENS
tENH
tENH
tENS
tENS
tENH
tENH
tDS
tDH
W1(1)
tENS
tENH
W2(1)
tENS
tENH
No Operation
NOTE:
1. Written to FIFO2.
Figure 4. Port-B Write Cycle Timing for FIFO2.
3022 drw 07
5.22
15