IDT723642 Просмотр технического описания (PDF) - Integrated Device Technology
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IDT723642 Datasheet PDF : 26 Pages
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IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1024 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
input-ready flag synchronizing clock. Therefore, an input-
ready flag is LOW if less than two cycles of the input-ready flag
synchronizing clock have elapsed since the next memory
write location has been read. The second LOW-to-HIGH
transition on the input-ready flag synchronizing Clock after the
read sets the input-ready flag HIGH.
A LOW-to-HIGH transition on an input-ready flag syn-
chronizing clock begins the first synchronization cycle of a
read if the clock transition occurs at time tSKEW1 or greater
after the read. Otherwise, the subsequent clock cycle can be
the first synchronization cycle (see Figures 9 and 10).
ALMOST-EMPTY FLAGS (AEA, AEB)
The almost-empty flag of a FIFO is synchronized to the
port clock that reads data from its array. The state machine
that controls an almost-empty flag monitors a write pointer and
read pointer comparator that indicates when the FIFO SRAM
status is almost empty, almost empty+1, or almost empty+2.
The almost-empty state is defined by the contents of register
X1 for AEB and register X2 for AEA. These registers are
loaded with preset values during a FIFO reset or programmed
from port A (see almost-empty flag and almost-full flag offset
programming above). An almost empty Flag is LOW when its
FIFO contains X or less words and is HIGH when its FIFO
contains (X+1) or more words. A data word present in the FIFO
output register has been read from memory.
Two LOW-to-HIGH transitions of the almost-empty flag
synchronizing clock are required after a FIFO write for its
almost-empty flag to reflect the new level of fill. Therefore, the
almost-full flag of a FIFO containing (X+1) or more words
remains LOW if two cycles of its synchronizing clock have not
elapsed since the write that filled the memory to the (X+1)
level. An almost-empty flag is set HIGH by the second LOW-
to-HIGH transition of its synchronizing clock after the FIFO
write that fills memory to the (X+1) level. A LOW-to-HIGH
transition of an almost-empty flag synchronizing clock begins
the first synchronization cycle if it occurs at time tSKEW2 or
greater after the write that fills the FIFO to (X+1) words.
Otherwise, the subsequent synchronizing clock cycle may be
the first synchronization cycle. (See Figures 11 and 12).
ALMOST-FULL FLAGS (AFA, AFB)
The almost-full flag of a FIFO is synchronized to the port
clock that writes data to its array. The state machine that
controls an almost-full flag monitors a write pointer and read
pointer comparator that indicates when the FIFO SRAM
status is almost full, almost full-1, or almost full-2. The almost-
full state is defined by the contents of register Y1 for AFA and
register Y2 for AFB. These registers are loaded with preset
values during a FlFO reset or programmed from port A (see
almost-empty flag and almost-full flag offset programming
above). An almost-full flag is LOW when the number of words
in its FIFO is greater than or equal to (256-Y), (512-Y), or
(1024-Y) for the IDT723622, IDT723632, or IDT723642 re-
spectively. An almost-full flag is HIGH when the number of
words in its FIFO is less than or equal to [256-(Y+1)], [512-
(Y+1)], or [1024-(Y+1)] for the IDT723622, IDT723632, or
IDT723642 respectively. Note that a data word present in the
FIFO output register has been read from memory.
Two LOW-to-HIGH transitions of the almost-full flag syn-
chronizing clock are required after a FIFO read for its almost-
full flag to reflect the new level of fill. Therefore, the almost-full
flag of a FIFO containing [256/512/1024-(Y+1)] or less words
remains LOW if two cycles of its synchronizing clock have not
elapsed since the read that reduced the number of words in
memory to [256/512/1024-(Y+1)]. An almost-full flag is set
HIGH by the second LOW-to-HIGH transition of its synchro-
nizing clock after the FIFO read that reduces the number of
words in memory to [256/512/1024-(Y+1)]. A LOW-to-HIGH
transition of an almost-full flag synchronizing clock begins the
first synchronization cycle if it occurs at time tSKEW2 or greater
after the read that reduces the number of words in memory to
[256/512/1024-(Y+1)]. Otherwise, the subsequent synchro-
nizing clock cycle may be the first synchronization cycle (see
Figures 13 and 14).
MAILBOX REGISTERS
Each FIFO has a 36-bit bypass register to pass command
and control information between port A and port B without
putting it in queue. The mailbox-select (MBA, MBB) inputs
choose between a mail register and a FIFO for a port data
transfer operation. A LOW-to-HIGH transition on CLKA writes
A0-A35 data to the mail1 register when a port-A write is
selected by CSA, W/RA, and ENA and with MBA HIGH. A
LOW-to-HIGH transition on CLKB writes BO-B35 data to the
mail2 register when a port-B write is selected by CSB, W/RB,
and ENB and with MBB HIGH. Writing data to a mail register
sets its corresponding flag (MBF1 or MBF2) LOW. Attempted
writes to a mail register are ignored while the mail flag is LOW.
When data outputs of a port are active, the data on the bus
comes from the FIFO output register when the port mailbox
select input is LOW and from the mail register when the port-
mailbox select input is HIGH. The mail1 register flag (MBF1 )
is set HIGH by a LOW-to-HIGH transition on CLKB when a
port-B read is selected by CSB, W/RB, and ENB and with MBB
HIGH. The mail2 register flag (MBF2) is set HIGH by a LOW-
to-HIGH transition on CLKA when a port-A read is selected by
CSA, W/RA, and ENA and with MBA HIGH. The data in a mail
register remains intact after it is read and changes only when
new data is written to the register.
5.22
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