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IDT723632L15PF
(Rev.:2015)

CMOS SyncBiFIFO 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

Integrated Device Technology 

IDT723622/723632/723642 CMOS SyncBiFIFO™

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

PIN DESCRIPTIONS

Symbol

Name

I/O

A0-A35 Port A Data

I/0

AEA

Port A Almost-

O

Empty Flag

(Port A)

AEB

Port B Almost-

O

Empty Flag

(Port B)

AFA

Port A Almost-

O

Full Flag

(Port A)

AFB

Port B Almost-

O

Full Flag

(Port B)

B0 - B35 Port B Data

I/O

CLKA

Port A Clock

I

CLKB

Port B Clock

I

CSA

Port A Chip

I

Select

CSB

Port B Chip

I

Select

ENA

Port A Enable

I

ENB

Port B Enable

I

FS1, FS0 FlagOffset

I

Selects

IRA

IRB

MBA

MBB

MBF1

Input Ready

Flag

Input Ready

Flag

Port A Mailbox

Select

Port B Mailbox

Select

Mail1 Register

Flag

O

(Port A)

O

(Port B)

I

I

O

MBF2

Mail2 Register

O

Flag

Description

36-bit bidirectional data port for side A.

Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words

in FIFO2 is less than or equal to the value in the Almost-Empty A Offset register, X2.

Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words

in FIFO1 is less than or equal to the value in the Almost-Empty B Offset register, X1.

Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty

locations in FIFO1 is less than or equal to the value in the Almost-Full A Offset register, Y1.

Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of empty

locations in FIFO2 is less than or equal to the value in the Almost-Full B Offset register, Y2.

36-bit bidirectional data port for side B.

CLKA is a continuous clock that synchronizes all data transfers through port A and can be

asynchronous or coincident to CLKB. IRA, ORA, AFA, and AEA are all synchronized to the

LOW-to-HIGH transition of CLKA.

CLKB is a continuous clock that synchronizes all data transfers through port B and can be

asynchronous or coincident to CLKA. IRB, ORB, AFB, and AEB are synchronized to the LOW-

to-HIGH transition of CLKB.

CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write on port A.

The A0-A35 outputs are in the high-impedance state when CSA is HIGH.

CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on

port B. The B0-B35 outputs are in the high-impedance state when CSB is HIGH.

ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A.

ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B.

The LOW-to-HIGH transition of a FlFO’s Reset input latches the values of FS0 and FS1.

If either FS0 or FS1 is HIGH when a Reset goes HIGH, one of three preset values is selected as

the offset for the FlFOs Almost-Full and Almost-Empty flags. If both FIFOs are reset simultaneously

and both FS0 and FS1 are LOW when RST1 and RST2 go HIGH, the first four writes to FIFO1

load the Almost-Empty and Almost-Full offsets for both FlFOs.

IRA is synchronized to the LOW-to-HIGH transition of CLKA. When IRA is LOW, FIFO1 is full

and writes to its array are disabled. IRA is set LOW when FIFO1 is reset and is set HIGH on the

second LOW-to-HIGH transition of CLKA after reset.

IRB is synchronized to the LOW-to-HIGH transition of CLKB. When IRB is LOW, FIFO2 is full

and writes to its array are disabled. IRB is set LOW when FIFO2 is reset and is set HIGH on the

second LOW-to-HIGH transition of CLKB after reset.

A HIGH level on MBA chooses a mailbox register for a port A read or write operation.

When the A0-A35 outputs are active, a HIGH level on MBA selects data from the mail2 register for

output and a LOW level selects FIFO2 output register data for output.

A HIGH level on MBB chooses a mailbox register for a port B read or write operation. When the

B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register or output and

a LOW level selects FIFO1 output register data for output.

MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1

register. Writes to the mail1 register are inhibited while MBF1 is LOW. MBF1 is set HIGH by

a LOW-to-HIGH transition of CLKB when a port B read is selected and MBB is HIGH. MBF1 is

set HIGH when FIFO1 is reset.

MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register.

Writes to the mail2 register are inhibited while MBF2 is LOW. MBF2 is set HIGH by a LOW-

to-HIGH transition of CLKA when a port A read is selected and MBA is HIGH. MBF2 is also

set HIGH when FIFO2 is reset.

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