IDT723632L15PF(2015) Просмотр технического описания (PDF) - Integrated Device Technology

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IDT723632L15PF
(Rev.:2015)

CMOS SyncBiFIFO 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

Integrated Device Technology 

IDT723622/723632/723642 CMOS SyncBiFIFO™

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

CLKB

ENB

AFB

tENS2

tENH

tPAF

[D-(Y2+1)] Words in FIFO2

(1)

tSKEW2

1

COMMERCIAL TEMPERATURE RANGE

2

tPAF

(D-Y2) Words in FIFO2

CLKA

tENS2

tENH

ENA

3022 drw 17

NOTES:

1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKB edge

and rising CLKA edge is less than tSKEW2, then AFB may transition HIGH one CLKB cycle later than shown.

2. FIFO2 write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.

3. D = Maximum FIFO Depth = 256 for the IDT723622, 512 for the IDT723632, 1,024 for the IDT723642.

Figure 15. Timing for AFB when FIFO2 is Almost-Full

CLKA

CSA

W/RA

MBA

ENA

A0 - A35

CLKB

MBF1

CSB

W/RB

MBB

ENB

B0 - B35

tENS1

tENS1

tENH

tENH

tENS2

tENS2

tENH

tENH

tDS

tDH

W1

tPMF

tPMF

tENS2

tENH

tEN

tMDV

tPMR

FIFO1 Output Register

tDIS

W1 (Remains valid in Mail1 Register after read)

3022 drw 18

Figure 16. Timing for Mail1 Register and MBF1 Flag

21

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