IDT723622L15PFG(2015) Просмотр технического описания (PDF) - Integrated Device Technology

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IDT723622L15PFG
(Rev.:2015)

CMOS SyncBiFIFO 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

Integrated Device Technology 

IDT723622/723632/723642 CMOS SyncBiFIFO™

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

CLKB

tEN2S

tENH

ENB

CLKA

AEA X2 Words in FIFO2

ENA

tSKEW2 (1)

1

2

tPAE

tPAE

(X2+1) Words in FIFO2

tENS2

tENH

3022 drw 15

NOTES:

1. tSKEW2 is the minimum time between a rising CLKB edge and a rising CLKA edge for AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge

and rising CLKA edge is less than tSKEW2, then AEA may transition HIGH one CLKA cycle later than shown.

2. FIFO2 Write (CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.

Figure 13. Timing for AEA when FIFO2 is Almost-Empty

CLKA

ENA

tENS2

AFA [D-(Y1+1)] Words in FIFO1

tENH

tPAF

(1)

tSKEW2

1

(D-Y1) Words in FIFO1

2

tPAF

CLKB

ENB

tENS2

tENH

3022 drw 16

NOTES:

1. tSKEW2 is the minimum time between a rising CLKA edge and a rising CLKB edge for AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge

and rising CLKB edge is less than tSKEW2, then AFA may transition HIGH one CLKA cycle later than shown.

2. FIFO1 Write (CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.

3. D = Maximum FIFO Depth = 256 for the IDT723622, 512 for the IDT723632, 1,024 for the IDT723642.

Figure 14. Timing for AFA when FIFO1 is Almost-Full

20

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