IDT723632(2015) Просмотр технического описания (PDF) - Integrated Device Technology

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IDT723632
(Rev.:2015)

CMOS SyncBiFIFO 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

Integrated Device Technology 

IDT723622/723632/723642 CMOS SyncBiFIFO™

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

CLKA

CSA

LOW

WRA

MBA

ENA

HIGH

tENS2

tENS2

tENH

tENH

tCLK

tCLKH tCLKL

COMMERCIAL TEMPERATURE RANGE

IRA HIGH tDS

tDH

A0 - A35

CLKB

W1

(1)

tSKEW1

tCLK

tCLKH tCLKL

1

2

ORB FIFO1 Empty

CSB LOW

3

tPOR

tPOR

W/RB

MBB

HIGH

LOW

tENS2

tENH

ENB

B0 - B35

tA

Old Data in FIFO1 Output Register

W1

4660 drw 10

NOTE:

1. tSKEW1 is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output register in three CLKB cycles.

If the time between the rising CLKA edge and rising CLKB edge is less than tSKEW1, then the transition of ORB HIGH and load of the first word to the output register may occur one CLKB

cycle later than shown.

Figure 8. ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty

16

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