IDT723622/723632/723642 CMOS SyncBiFIFO™
256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2
CLKB
tCLKH
tCLK
tCLKL
COMMERCIAL TEMPERATURE RANGE
ORB HIGH
CSB
W/RB
MBB
ENB
B0 - B35
NOTE:
1. Read From FIFO1.
tENS2
tMDV
tEN
tENH
tA
W1(1)
tENS2
tENH
tA
W2(1)
Figure 6. Port B Read Cycle Timing for FIFO1
tENS2
tENH
No Operation
W3 (1)
tDIS
3022 drw 08
CLKA
ORA
CSA
tCLKH
tCLK
tCLKL
W/RA
MBA
ENA
A0 - A35
NOTE:
1. Read From FIFO2.
tENS2
tDMV
tEN
tENH
tA
W1(1)
tENS2
tENH
tA
W2(1)
Figure 7. Port A Read Cycle Timing for FIFO2
15
tENS2
tENH
No Operation
W3(1)
tDIS
3022 drw 09