IDT723622L15PF(2015) Просмотр технического описания (PDF) - Integrated Device Technology

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IDT723622L15PF
(Rev.:2015)

CMOS SyncBiFIFO 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

Integrated Device Technology 

IDT723622/723632/723642 CMOS SyncBiFIFO™

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

CLKA

CLKB

RST1

tRSTS

tFSS

tRSTH

tFSH

FS1,FS0

tPIR

IRA

ORB

AEB

tRSF

AFA

tRSF

tRSF

MBF1

NOTE:

1. FIFO2 is reset in the same manner to load X2 and Y2 with a preset value.

0,1

tPOR

tPIR

3022 drw 04

Figure 2. FIFO1 Reset and Loading X1 and Y1 with a Preset Value of Eight(1)

CLKA

4

1

2

tFSS

RST1,

RST2

tFSH

FS1,FS0

0,0

tPIR

IRA

tENS2

tENH

tSKEW1(1)

ENA

A0 - A35

tDH

tDS

AFA Offset

(Y1)

AEB Offset

(X1)

AFB Offset

(Y2)

AEA Offset

(X2)

First Word to FIFO1

CLKB

1

2

tPIR

IRB

3022 drw 05

NOTES:

1. tSKEW1 is the minimum time between the rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA and

rising edge of CLKB is less than tSKEW1, then IRB may transition HIGH one CLKB cycle later than shown.

2. CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program offset register on consecutive clock cycles.

Figure 3. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset

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