IDT723632L15PF8(2015) Просмотр технического описания (PDF) - Integrated Device Technology

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IDT723632L15PF8
(Rev.:2015)

CMOS SyncBiFIFO 256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

Integrated Device Technology 

IDT723622/723632/723642 CMOS SyncBiFIFO™

256 x 36 x 2, 512 x 36 x 2, 1,024 x 36 x 2

COMMERCIAL TEMPERATURE RANGE

timing diagrams for port B can be found in Figure 5 and 6.

The setup and hold time constraints to the port Clocks for the port Chip

Selects and Write/Read selects are only for enabling write and read

operations and are not related to high-impedance control of the data

outputs. If a port enable is LOW during a clock cycle, the port’s Chip Select

and Write/Read select may change states during the setup and hold time

window of the cycle.

When a FIFO Output Ready flag is LOW, the next word written is

automatically sent to the FIFO output register automatically by the LOW-to-HIGH

transition of the port clock that sets the Output Ready flag HIGH. When the Output

Ready flag is HIGH, subsequent data is clocked to the output registers only when

a FIFO read is selected using the port’s Chip Select, Write/Read select, Enable,

and Mailbox select.

SYNCHRONIZED FIFO FLAGS

Each FIFO is synchronized to its port clock through at least two flip-flop

stages. This is done to improve flag-signal reliability by reducing the

probability of metastable events when CLKA and CLKB operate asynchro-

nously to one another. ORA, AEA, IRA, and AFA are synchronized to CLKA.

ORB, AEB, IRB, and AFB are synchronized to CLKB. Tables 4 and 5 show

the relationship of each port flag to FIFO1 and FIFO2.

OUTPUT READY FLAGS (ORA, ORB)

The Output Ready flag of a FIFO is synchronized to the port clock that

reads data from its array. When the Output Ready flag is HIGH, new data

is present in the FIFO output register. When the Output Ready flag is LOW,

the previous data word is present in the FIFO output register and attempted FIFO

reads are ignored.

A FIFO read pointer is incremented each time a new word is clocked to

its output register. The state machine that controls an Output Ready flag monitors

a write pointer and read pointer comparator that indicates when the FIFO

memory status is empty, empty+1, or empty+2. From the time a word is written

to a FIFO, it can be shifted to the FIFO output register in a minimum of three cycles

of the Output Ready flag synchronizing clock. Therefore, an Output Ready flag

is LOW if a word in memory is the next data to be sent to the FlFO output register

and three cycles of the port Clock that reads data from the FIFO have not elapsed

since the time the word was written. The Output Ready flag of the FIFO remains

LOW until the third LOW-to-HIGH transition of the synchronizing clock occurs,

simultaneously forcing the Output Ready flag HIGH and shifting the word to the

FIFO output register.

A LOW-to-HIGH transition on an Output Ready flag synchronizing clock

begins the first synchronization cycle of a write if the clock transition occurs at

time tSKEW1 or greater after the write. Otherwise, the subsequent clock cycle can

be the first synchronization cycle (see Figures 8 and 9 for ORA and ORB timing

diagrams).

INPUT READY FLAGS (IRA, IRB)

The Input Ready flag of a FlFO is synchronized to the port clock that writes

data to its array. When the Input Ready flag is HIGH, a memory location is free

in the FIFO to receive new data. No memory locations are free when the Input

Ready flag is LOW and attempted writes to the FIFO are ignored.

Each time a word is written to a FIFO, its write pointer is incremented. The

state machine that controls an Input Ready flag monitors a write pointer and read

TABLE 2 — PORT A ENABLE FUNCTION TABLE

CSA W/RA ENA MBA CLKA

Data A (A0-A35) I/O

H

X

X

X

X

High-Impedance

L

H

L

X

X

Input

L

H

H

L

↑

Input

L

H

H

H

↑

Input

L

L

L

L

X

Output

L

L

H

L

↑

Output

L

L

L

H

X

Output

L

L

H

H

↑

Output

TABLE 3 — PORT B ENABLE FUNCTION TABLE

CSB W/RB ENB MBB CLKB

H

X

X

X

X

L

L

L

X

X

L

L

H

L

↑

L

L

H

H

↑

L

H

L

L

X

L

H

H

L

↑

L

H

L

H

X

L

H

H

H

↑

Data B (B0-B35) I/O

High-Impedance

Input

Input

Input

Output

Output

Output

Output

10

PORT FUNCTION

None

None

FIFO1 write

Mail1 write

None

FIFO2 read

None

Mail2 read (set MBF2 HIGH)

PORT FUNCTION

None

None

FIFO2 write

Mail2 write

None

FIFO1 read

None

Mail1 read (set MBF1 HIGH)

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