IDT72615L50J Просмотр технического описания (PDF) - Integrated Device Technology

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IDT72615L50J

CMOS SyncBiFIFO 256 x 18 x 2 and 512 x 18 x 2

Integrated Device Technology 

IDT72605/IDT72615 CMOS SyncBiFIFO

256 x 18 x 2 and 512 x 18 x 2

CLKB

COMMERCIAL TEMPERATURE RANGE

R/WB

tCS

ENB

tDS

DB0 -DB17

D0 (First valid write)

D1

D2

D3

tSKEW1

tFRL

(1)

CLKA

A0 , A1 , A2 ,

R/WA

CSA , ENA

EFBA

DA0 -DA17

OE A

tEF

tOLZ

tCS

tA

tOE

tA

D0

NOTE:

1. When tSKEW1 ≥ minimum specification, tFRL(Max.) = tCLK + tSKEW1

tSKEW1 < minimum specification, tFRL(Max.) = 2tCLK + tSKEW1

The Latency Timing apply only at the Empty Boundary (EF = LOW).

Figure 9. B→A First Data Word Latency after Reset for Simultaneous Read and Write

D1

2704 drw 13

5.18

15

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