IDT72605L35J(2013) Просмотр технического описания (PDF) - Integrated Device Technology

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IDT72605L35J
(Rev.:2013)

CMOS SyncBiFIFO 256 x 18 x 2 512 x 18 x 2

Integrated Device Technology 

IDT72605/72615 CMOS SYNCBiFIFO™

256 x 18x 2 and 512 x 18 x 2

CLKA

A0, A1, A2

A2, A1, A0 = 001

INDUSTRIAL TEMPERATURE RANGE

tCS

R/WA

CSA

ENA

FFAB

DA0-DA17

CLKB

tCS

tCH

tFF

tDS

DATA INPUT

tSKEW1

tFF

BYPASS FLAG

tSKEW1

tCH

tFF

FIFO FLAG

tSKEW1

R/WB

ENB

EFAB

tEF

FIFO FLAG

tCS

tEF

tEF

BYPASS FLAG

FIFO FLAG

BYPB

DB0-DB17

OEB

tA

tOLZ

tOE

DATA OUTPUT

tOHZ

2704 drw 13

NOTES:

1. When CSA is brought HIGH, A→B Bypass mode will switch to FIFO mode on the following CLKA LOW-to-HIGH transition.

2. After the bypass operation is completed, the BYPB goes from LOW-to-HIGH; this will reset all bypass flags. The bypass path becomes available for the next bypass

operation.

3. When A-side changed from bypass mode into FIFO mode, B-side only has one cycle to read the bypass data. On the next cycle, B-side will be forced back to FIFO

mode.

Figure 10. A→B Bypass Timing

13

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