IDT72605/72615 CMOS SYNCBiFIFO™
256 x 18x 2 and 512 x 18 x 2
CLKB
tCLKH
tCLK
tCLKL
INDUSTRIAL TEMPERATURE RANGE
R/WB
ENB
EFBA
DB0-DB17
OEB
CLKA
tCS
tCH
NO OPERATION
tEF
tEF
tOLZ
tA
tOE
VALID DATA
tOHZ
tSKEW1
NO WRITE OPERATION
Figure 7. Port B (A→B) Read Timing
WRITE
2704 drw 10
CLKA
A0, A1, A2
R/WA
CSA, ENA
tCS
tDS
DA0-DA17
D0 (First Valid Write)
D1
D2
tSKEW1
tFRL
(1)
CLKB
R/WB
ENB
EFAB
DB0-DB17
OEB
tEF
tOLZ
tCS
tA
tOE
tA
D0
NOTE:
1. When tSKEW1 ≥ minimum specification, tFRL(Max.) = tCLK + tSKEW1
tSKEW1 < minimum specification, tFRL(Max.) = 2tCLK + tSKEW1 or tCLK + tSKEW1
The Latency Timing applies only at the Empty Boundary (EF = LOW).
Figure 8. A→B First Data Word Latency after Reset for Simultaneous Read and Write
11
D3
D1
2704 drw 11