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IDT72261L12PFB

CMOS SUPERSYNC FIFO™ 16,384 x 9, 32,768 x 9

Integrated Device Technology 

IDT72261/72271 SyncFIFO™

16,384 x 9, 32,768 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

When OR goes LOW, Retransmit Setup is complete; at the

same time, the contents of the first location are automatically

displayed on the outputs. Since FWFT Mode is selected, the

first word appears on the outputs, no read request necessary.

Reading all subsequent words requires a LOW on REN to

enable the rising edge of RCLK. Writing operations can begin

after one of two conditions have been met: OR is LOW or 14

cycles of the faster clock (RCLK or WCLK) have elapsed since

the RCLK rising edge enabled by the RT pulse.

The assertion time of OR during Retransmit Setup is

variable. The parameter tRTF2, which is measured from the

rising RCLK edge enabled by RT to the falling edge of OR is

described by the following equation:

tRTF2 max. = 14*Tf + 4*TRCLK (in ns)

where Tf is either the RCLK or the WCLK period, whichever

is shorter, and TRCLK is the RCLK period. Note that a

Retransmit Setup in FWFT mode requires one more RCLK

cycle than in IDT Standard mode.

Regarding IR: Note that since no more than Full - 2 writes

are allowed between a Reset and a Retransmit Setup, IR will

remain LOW throughout the setup procedure.

For FWFT mode, updating the PAE, HF, and PAF flags

begins with the "last" rising edge of RCLK before the end of

Retransmit Setup. This is the same edge that asserts OR and

automatically accesses the first memory location. Note that,

in this case, REN is not required to initiate flag updating. HF

is updated on the "last" RCLK rising edge. PAE is updated

after two more rising RCLK edges. PAF is updated after the

"last" rising RCLK edge, followed by the next two rising WCLK

edges. (If the tskew2 specification is not met, add one more

WCLK cycle.)

RT is synchronized to RCLK. The Retransmit operation is

useful in the event of a transmission error on a network, since

it allows a data packet to be resent.

FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)

This is a dual purpose pin. During Master Reset, the state

of the FWFT/SI helps determine whether the device will

operate in IDT Standard mode or First Word Fall Through

(FWFT) mode.

If, at the time of Master Reset, FWFT/SI is LOW, then IDT

Standard mode will be selected. This mode uses the Empty

Flag (EF) to indicate whether or not there are any words

present in the FIFO memory. It also uses the Full Flag function

(FF) to indicate whether or not the FIFO memory has any free

space for writing. In IDT Standard mode, every word read

from the FIFO, including the first, must be requested using the

Read Enable (REN) line.

If, at the time of Master Reset, FWFT/SI is HIGH, then

FWFT mode will be selected. This mode uses Output Ready

(OR) to indicate whether or not there is valid data at the data

outputs (Qn). It also uses Input Ready (IR) to indicate whether

or not the FIFO memory has any free space for writing. In the

FWFT mode, the first word written to an empty FIFO goes

directly to Qn, no read request necessary. Subsequent words

must be accessed using the Read Enable (REN) line.

After Master Reset, FWFT/SI acts as a serial input for

loading PAE and PAF offsets into the programmable registers.

The serial input function can only be used when the serial

loading method has been selected during Master Reset.

FWFT/SI functions the same way in both IDT Standard and

FWFT modes.

WRITE CLOCK (WCLK)

A write cycle is initiated on the rising edge of the write clock

(WCLK). Data set-up and hold times must be met with respect

to the LOW-to-HIGH transition of the WCLK. The write and

read clocks lines can either be asynchronous or coincident.

WRITE ENABLE (WEN)

When Write Enable (WEN) is LOW, data can be loaded into

the input register on the rising edge of every WCLK cycle.

Data is stored in the RAM array sequentially and indepen-

dently of any on-going read operation.

When WEN is HIGH, the input register holds the previous

data and no new data is loaded into the FIFO.

To prevent data overflow in the IDT Standard Mode, FF will

go LOW , inhibiting further write operations. Upon the comple-

tion of a valid read cycle, FF will go HIGH allowing a write to

occur. WEN is ignored when the FIFO is full.

To prevent data overflow in the FWFT mode, IR will go

HIGH, inhibiting further write operations. Upon the completion

of a valid read cycle, IR will go LOW allowing a write to occur.

WEN is ignored when the FIFO is full.

READ CLOCK (RCLK)

Data can be read on the outputs, on the rising edge of the

read clock (RCLK), when Output Enable (OE) is set LOW. The

write and read clocks can be asynchronous or coincident.

READ ENABLE (REN)

When Read Enable (REN) is LOW, data is loaded from the

RAM array into the output register on the rising edge of the

RCLK.

When REN is HIGH, the output register holds the previous

data and no new data is loaded into the output register.

In the IDT Standard Mode, every word accessed at Qn,

including the first word written to an empty FIFO, must be

requested using REN. When all the data has been read from

the FIFO, the Empty Flag (EF) will go LOW, inhibiting further

read operations. REN is ignored when the FIFO is empty.

Once a write is performed, EF will go HIGH after tFWL1 +tREF

and a read is permitted.

In the FWFT Mode, the first word written to an empty FIFO

automatically goes to the outputs Qn, no need for any read

request. In order to access all other words, a read must be

executed using REN . When all the data has been read from

the FIFO, Output Ready (OR) will go HIGH, inhibiting further

read operations. REN is ignored when the FIFO is empty.

Once a write is performed, OR will go LOW after tFWL2 +tREF,

when the first word appears at Qn ; if a second word is written

into the FIFO, then REN can be used to read it out.

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