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IDT72271L20PFB

CMOS SUPERSYNC FIFO™ 16,384 x 9, 32,768 x 9

Integrated Device Technology 

IDT72261/72271 SyncFIFO™

16,384 x 9, 32,768 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN DESCRIPTION

Symbol

D0–D8

MRS

Name

I/O

Data Inputs

I

Master Reset

I

PRS

Partial Reset

I

RT

FWFT/SI

WCLK

WEN

RCLK

REN

OE

SEN

LD

Retransmit

I

First Word Fall

I

Through/Serial In

Write Clock

I

Write Enable

I

Read Clock

I

Read Enable

I

Output Enable

I

Serial Enable

I

Load

I

FS

FF/IR

EF/OR

PAF

PAE

HF

Q0–Q8

VCC

GND

Frequency Select I

Full Flag/

O

Input Ready

Empty Flag/

O

Output Ready

Programmable O

Almost Full Flag

Programmable O

Almost Empty Flag

Half-full Flag

O

Data Outputs

O

Power

Ground

Description

Data inputs for a 9-bit bus.

MRS initializes the read and write pointers to zero and sets the output register to

all zeroes. During Master Reset, the FIFO is configured for either FWFT or IDT

Standard Mode, one of two programmable flag default settings, and serial or

parallel programming of the offset settings.

PRS initializes the read and write pointers to zero and sets the output register to

all zeroes. During Partial Reset,the existing mode (IDT or FWFT), programming

method (serial or parallel), and programmable flag settings are all retained.

Allows data to be resent starting with the first location of FIFO memory.

During Master Reset, selects First Word Fall Through or IDT Standard mode.

After Master Reset, this pin functions as a serial input for loading offset registers

When enabled by WEN, the rising edge of WCLK writes data into the FIFO and

offsets into the programmable registers.

WEN enables WCLK for writing data into the FIFO memory and offset registers.

When enabled by REN, the rising edge of RCLK reads data from the FIFO

memory and offsets from the programmable registers.

REN enables RCLK for reading data from the FIFO memory and offset registers.

OE controls the output impedance of Qn

SEN enables serial loading of programmable flag offsets

During Master Reset, LD selects one of two partial flag default offsets (127 and

1023) and determines programming method, serial or parallel. After Master

Reset, this pin enables writing to and reading from the offset registers.

The FS setting optimizes data flow through the FIFO.

In the IDT Standard Mode, the FF function is selected. FF indicates whether or

not the FIFO memory is full. In the FWFT mode, the IR function is selected. IR

indicates whether or not there is space available for writing to the FIFO memory.

In the IDT Standard Mode, the EF function is selected. EF indicates whether or

not the FIFO memory is empty. In FWFT mode, the OR function is selected.

OR indicates whether or not there is valid data available at the outputs.

PAF goes HIGH if the number of free locations in the FIFO memory is more than

offset m which is store in Almost Full which is stored in the Full Offset register. PAF

goes LOW if the number of free locations in the FIFO memory is less than m.

PAE goes LOW if the number of words in the FIFO memory is less than offset n

which is stored in theEmpty Offset register. PAE goes HIGH if the number of

words in the FIFO memory is greater than offset n.

HF indicates whether the FIFO memory is more or less than half-full.

Data outputs for a 9-bit bus.

+5 volt power supply pins.

Ground pins.

3097 tbl 01

4

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