IDT72271L12TFB Просмотр технического описания (PDF) - Integrated Device Technology

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IDT72271L12TFB

CMOS SUPERSYNC FIFO™ 16,384 x 9, 32,768 x 9

Integrated Device Technology 

IDT72261/72271 SyncFIFO™

16,384 x 9, 32,768 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

The Retransmit function allows the read pointer to be reset

to the first location in the RAM array. It is synchronized to

RCLK when RT is LOW. This feature is convenient for

sending the same data more than once.

If, at any time, the FIFO is not actively performing a function,

the chip will automatically power down. This occurs if neither

a read nor a write occurs within 10 cycles of the faster clock,

RCLK or WCLK. During the Power Down state, supply current

consumption (ICC2) is at a minimum. Initiating any operation

(by activating control inputs) will immediately take the device

out of the Power Down state.

The IDT72261/72271 are depth expandable. The addition

of external components is unnecessary. The IR and OR

functions, together with REN and WEN, are used to extend the

total FIFO memory capacity.

The FS line ensures optimal data flow through the FIFO. It

is tied to GND if the RCLK frequency is higher than the WCLK

frequency or to Vcc if the RCLK frequency is lower than the

WCLK frequency

The IDT72261/72271 is fabricated using IDT’s high speed

submicron CMOS technology.

PIN CONFIGURATIONS (CONT.)

11

DNC Q5 VCC Q2 Q1 GND D1 D3 D5

10 Q6 GND Q4 Q3 GND Q0 D0 D2 D4 D6 D7

09 Q8 Q7

D GND(2)

8

08 DNC DNC

07 DNC GND

GND(2) GND(2)

(2)

GND

GND(2)

06 DNC DNC

GND(2)

(2)

GND

05 DNC VCC

04 GND DNC

Pin 1 Designator

GND(2) GND(2)

VCC VCC

03 DNC DNC

SEN FS

02 DNC OE REN GND PAE

HF

FF/

IR

DNC

LD

WCLK WEN

01

RT

RCLK

EF/

OR

VCC

PAF GND

FWFT/

SI

MRS PRS

A B CDE F GHJ K L

PGA (G68-1, order code: G)

TOP VIEW

3036 drw 03

NOTES:

1. DNC = Do not connect.

2. This pin may either be tied to ground or left open.

3

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