IDT72261L10G Просмотр технического описания (PDF) - Integrated Device Technology

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IDT72261L10G

CMOS SUPERSYNC FIFO™ 16,384 x 9, 32,768 x 9

Integrated Device Technology 

IDT72261/72271 SyncFIFO™

16,384 x 9, 32,768 x 9

WCLK

tDS

D0 - D8

tENS

WEN

RCLK

EF

DATA WRITE 1

tENH

tFWL1(1)

tREF

REN

MILITARY AND COMMERCIAL TEMPERATURE RANGES

tDS

tENS

DATA WRITE 2

tENH

tREF

(1)

tFWL1

tREF

OE

LOW

tA

Q0 - Q8

DATA IN OUTPUT REGISTER

NOTES:

1. tFWL1 max. (in ns) = 10*Tf + 2*TRCLK

Where Tf is either the RCLK or the WCLK period, whichever is shorter, and TRCLK is the period.

2. LD = HIGH

Figure 10. Empty Flag Timing (IDT Standard Mode)

WORD 1

3036 drw 13

20

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