IDT72261/72271 SyncFIFO™
16,384 x 9, 32,768 x 9
WCLK
NO WRITE
1
tSKEW1 (1)
D0 - D8
FF
WEN
2
tDS
tWFF
Wd
tWFF
MILITARY AND COMMERCIAL TEMPERATURE RANGES
NO WRITE
1
tSKEW1 (1)
2
DATA tDS
WRITE
tWFF
RCLK
REN
tENS
tENH
tENS
tENH
OE LOW
tA
tA
Q0 - Q8 DATA IN OUTPUT REGISTER
DATA READ
NEXT DATA READ
3036 drw 12
NOTES:
1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go high (after one WCLK cycle pus tWFF).
If the time between the rising edge of the RCLK and the rising edge of the WCLK is less than tSKEW1, then the FF deassertion may be delayed an extra
WCLK cycle.
2. LD = HIGH
Figure 9. Full Flag Timing (IDT Standard Mode)
19