IDT72261L12G Просмотр технического описания (PDF) - Integrated Device Technology

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IDT72261L12G

CMOS SUPERSYNC FIFO™ 16,384 x 9, 32,768 x 9

Integrated Device Technology 

IDT72261/72271 SyncFIFO™

16,384 x 9, 32,768 x 9

WCLK

tCLK

tCLKH

1

tCLKL

D0 - D8

WEN

FF

RCLK

tSKEW(11)

MILITARY AND COMMERCIAL TEMPERATURE RANGES

2

tDS tDH

DATAIN VALID

tENS tENH

tWFF

tWFF

NO OPERATION

REN

3036 drw 09

NOTES:

1. tSKEW1 is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that FF will go HIGH (after one WCLK cycle plus tWFF).

If the time between the rising edge of RCLK and the rising edge of WCLK is less than tSKEW1, then the FF deassertion may be delayed an extra WCLK

cycle.

2. LD = HIGH

Figure 6. Write Cycle Timing (IDT Standard Mode)

16

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