IDT72261L15GB Просмотр технического описания (PDF) - Integrated Device Technology

Номер в каталоге

Компоненты Описание

Список матч

IDT72261L15GB

CMOS SUPERSYNC FIFO™ 16,384 x 9, 32,768 x 9

Integrated Device Technology 

IDT72261/72271 SyncFIFO™

16,384 x 9, 32,768 x 9

MILITARY AND COMMERCIAL TEMPERATURE RANGES

LOW, then m = 07FH and the PAF switching threshold is 127

words from the Full boundary, if LD is HIGH, then m = 3FFH

and the PAF switching threshold is 1023 words away from the

Full boundary.

Any integral value of m from 0 to the maximum FIFO depth

minus 1 (16,383 words for the 72261, 32,767 words for the

72271) can be programmed into the Full Offset register.

In IDT Standard Mode, if no reads are performed after reset

(MRS or PRS), PAF will go LOW after (16,384-m) writes to the

IDT72261, and (32,768-m) writes to the IDT72271.

In FWFT Mode, if no reads are performed after reset (MRS

or PRS), PAF will go LOW after (16,385-m) writes to the

IDT72261, and (32,769-m) writes to the IDT72271. In this

case, the first word written to an empty FIFO does not stay in

memory, but goes unrequested to the output register; there-

fore, it has no effect on determining the state of PAF.

Note that even though PAF is programmed to switch LOW

during the first word latency period (tFWL), attempts to read

data will be ignored until EF goes HIGH indicating that data is

available at the output port. This is true for both timing modes.

PAF is synchronous and updated on the rising edge of

WCLK. It is double-registered to enhance metastable immu-

nity.

PROGRAMMABLE ALMOST-EMPTY FLAG (PAE)

The Programmable Almost-Empty Flag (PAE) will go LOW

when the FIFO reaches the Almost-Empty condition as speci-

fied by the offset n stored in the Empty Offset register.

At the time of Master Reset, depending on the state of LD,

one of two possible default offset values are chosen. If LD is

LOW, then n = 07FH and the PAE switching threshold is 127

words from the Empty boundary, if LD is HIGH, then n = 3FFH

and the PAE switching threshold is 1023 words away from the

Empty boundary.

Any integral value of n from 0 to the maximum FIFO depth

minus 1 (16,383 words for the 72261, 32,767 words for the

72271) can be programmed into the Empty Offset register.

In IDT Standard Mode, if no reads are performed after reset

(MRS or PRS), PAE will go HIGH after (n + 1) writes to the

IDT72261/72271.

In FWFT Mode, if no reads are performed after reset (MRS

or PRS), PAE will go HIGH after (n+2) writes to the IDT72261/

72271. In this case, the first word written to an empty FIFO

does not stay in memory, but goes unrequested to the output

register; therefore, it has no effect on determining the state of

PAE.

Note that even though PAE is programmed to switch HIGH

during the first word latency period (tFWL), attempts to read

data will be ignored until EF goes HIGH indicating that data is

available at the output port. This is true for both timing modes.

PAE is synchronous and updated on the rising edge of

RCLK. It is double-registered to enhance metastable immu-

nity.

HALF-FULL FLAG (HF)

This output indicates a half-full memory. The rising WCLK

edge that fills the memory beyond half-full sets HF LOW. The

flag remains LOW until the difference between the write and

read pointers becomes less than or equal to one half of the

total depth of the device, the rising RCLK edge that accom-

plishes this condition also sets HF HIGH.

In IDT Standard Mode, if no reads are performed after reset

(MRS or PRS), HF will go LOW after (D/2 + 1) writes, where D

is the maximum FIFO depth ( 16,384 words for the IDT72261,

32,768 words for the IDT72271).

In FWFT Mode, if no reads are performed after reset (MRS

or PRS), HF will go LOW after (D/2+2) writes to the IDT72261/

72271. In this case, the first word written to an empty FIFO

does not stay in memory, but goes unrequested to the output

register; therefore, it has no effect on determining the state of

HF.

Because HF uses both RCLK and WCLK for synchroniza-

tion purposes, it is asynchronous.

DATA OUTPUTS (Q0-Q8)

Q0-Q8 are data outputs for 9-bit wide data.

13

Share Link: