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TMC3533 Просмотр технического описания (PDF) - Fairchild Semiconductor

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TMC3533

Triple Video D/A Converter 8 bit, 80 Msps, 3.3V

Fairchild Semiconductor

TMC3533 Datasheet PDF : 12 Pages

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PRODUCT SPECIFICATION

TMC3533

Application Notes

Figure 4 illustrates a typical TMC3533 interface circuit. In

this example, an optional 1.2 Volt bandgap reference is con-

nected to the VREF output, overriding the internal voltage

reference source.

Grounding

It is important that the TMC3533 power supply is well-regu-

lated and free of high-frequency noise. Careful power supply

decoupling will ensure the highest quality video signals at

the output of the circuit. The TMC3533 has separate analog

and digital circuits. To keep digital system noise from the

D/A converter, it is recommended that power supply voltages

(VDD) come from the system analog power source and all

ground connections (GND) be made to the analog ground

plane. Power supply pins should be individually decoupled

at the pin.

Printed Circuit Board Layout

Designing with high-performance mixed-signal circuits

demands printed circuits with ground planes. Overall system

performance is strongly inﬂuenced by the board layout.

Capacitive coupling from digital to analog circuits may

result in poor D/A conversion. Consider the following sug-

gestions when doing the layout:

1. Keep the critical analog traces (VREF, IREF, COMP,

IOS, IOR, IOG, IOB) as short as possible and as far as

possible from all digital signals. The TMC3533 should

be located near the board edge, close to the analog out-

put connectors.

2. The power plane for the TMC3533 should be separate

from that which supplies the digital circuitry. A single

power plane should be used for all of the VDD pins. If

the power supply for the TMC3533 is the same as that of

the system's digital circuitry, power to the TMC3533

should be decoupled with 0.1µF and 0.01µF capacitors

and isolated with a ferrite bead.

3. The ground plane should be solid, not cross-hatched.

Connections to the ground plane should have very short

leads.

4. If the digital power supply has a dedicated power plane

layer, it should not be placed under the TMC3533, the

voltage reference, or the analog outputs. Capacitive cou-

pling of digital power supply noise from this layer to the

TMC3533 and its related analog circuitry can have an

adverse effect on performance.

5. CLK should be handled carefully. Jitter and noise on

this clock will degrade performance. Terminate the

clock line carefully to eliminate overshoot and ringing.