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IDT72141

CMOS PARALLEL-TO-SERIAL FIFO 2048 X 9 4096 X 9

Integrated Device Technology 

IDT72131, IDT72141

CMOS PARALLEL-TO-SERIAL FIFO 2048 x 9 & 4096 x 9

COMMERCIAL TEMPERATURE RANGES

Width Expansion Configuration

In the cascaded case, word widths of more than 9 bits can

be achieved by using more than one device. By tying the SOX

line of the least significant device HIGH and the SOX of the

subsequent devices to the appropriate Data Set lines of the

previous devices, a cascaded serial word is achieved.

On the first LOW-to-HIGH clock edge of SOCP, all lines go

LOW. Just as in the standalone case, on each corresponding

clock cycle, the equivalent Data Set line goes HIGH in order

of least to most significant. When the Data Set line which is

connected to the SOX input of the next device goes HIGH, the

D0 of that device goes HIGH, the cascading from one device

to the next. The Data Set line of the most significant bit

programs the serial word width by being connected to all NR

inputs.

The Serial Data Output (SO) of each device in the serial

word must be tied together. Since the SO pin is three stated,

only the device which is currently shifting out is enabled and

driving the 1-bit-bus.

SERIAL OUTPUT CLOCK

V CC

9

GND

D 0-8

SO

SOCP

SOX

NR

XI

FIFO #1

Q8

PARALLEL DATA IN

16-BITS WIDE

SERIAL DATA

7

OUTPUT

D 0-6

SO

SOCP

SOX

NR

GND

XI

FIFO #2

Q6

0

1

7

8

9

10

14

15

0

SOCP

Q 8 OF FIFO #1 AND

SOX OF FIFO #2

Q6 OF FIFO #2 AND

NR OF FIFO #1 AND

FIFO #2

2751 drw 16

Figure 13. Width Wxpansion for 16-bit Parallel Data In. The Parallel Data In is tied to D0-8 of FIFO #1 and D0-6 of FIFO #2.

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