RP5C62 Просмотр технического описания (PDF) - RICOH Co.,Ltd.

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RP5C62

REAL-TIME CLOCK

RICOH Co.,Ltd. 

RP/RF/RS5C62

2.9 Timer Clock Selection Register (BANK1 at “Ch”)

D3

D2

D1

D0

TM3

TM2

TM1

TM0 (For write operation)

TM3

0

0

TMFG (For read operation) *1

Timer counter cycle setting bit (TM3 to TM0) *2

Timer output indication bit (TMFG) *3

*1) Only the TM3 bit is intended for read operation. The D0 bit is always read as “TMFG”. The D2 and D1 bits are always read as “0”.

*2) The TM3 to TM0 bits are used to set cycles for the counters as shown in the table below.

TM3

TM2

0

*

1

0

1

0

1

0

1

0

1

1

1

1

1

1

1

1

TM1

TM0

T1

T2

T3

(Watchdog timer cycle) (Output time after timer resetting) (Free-running timer cycle)

Timer output disabled Timer output disabled Timer output disabled

*

*

(TMOUT pin output turned off) (TMOUT pin output turned off) (TMOUT pin output turned off)

0

0

0

1

1

0

1

1

0

0

0

1

1

0

1

1

562ms

281ms

140ms

70.3ms

35.1ms

17.5ms

8.78ms

4.39ms

562 to 626ms

281 to 313ms

140 to 157ms

70.3 to 78.2ms

35.1 to 39.1ms

17.5 to 19.6ms

8.78 to 9.77ms

4.39 to 4.89ms

625ms

312.5ms

156.3ms

78.13ms

39.06ms

19.53ms

9.766ms

4.883ms

T1 : Maximum time during which timer output is disabled after timer resetting.

(Timer reset occurs upon setting the TMR bit to “1” in the control register 1.)

(Timer output occurs upon driving low the TMOUT pin output.)

T2 : Time between timer output and cycle setting during timer resetting (upon setting the TM3 bit to “0” ),

or timer resetting, or transition of the CE pin input from its low to high levels.

T3 : Timer output cycle without timer reset.

14

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