RF5C62 Просмотр технического описания (PDF) - RICOH Co.,Ltd.

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RF5C62

REAL-TIME CLOCK

RICOH Co.,Ltd. 

RP/RF/RS5C62

FUNCTIONAL DESCRIPTION

1. Addressing

Address Bus

BANK 0 (BANK=0)

BANK 1 (BANK=1)

A3 A2 A1 A0

Description

D3

D2

D1

D0

Description

D3

D2

D1

D0

0 0 0 0 0 1 sec. Counter R/W S8

S4

S2

S1 Cyclic interrupt select Reg. W/O CT3 CT2 CT1 CT0

1 0 0 0 1 10 sec. Counter R/W

S40 S20 S10 Adust Reg.

W/O

ADJ

2 0 0 1 0 1 min. Counter R/W M8 M4 M2 M1 1 min. alarm Reg.

R/W AM8 AM4 AM2 AM1

3 0 0 1 1 10 min. Counter R/W

M40 M20 M10 10 min. alarm Reg.

R/W

AM40 AM20 AM10

4 0 1 0 0 1 hour Counter R/W H8 H4 H2 H1 1 hour alarm Reg.

R/W AH8 AH4 AH2 AH1

5 0 1 0 1 10 hour Counter R/W

P/A

H10 10 hour alarm Reg.

or H20

6 0 1 1 0 day-of-the-week Counter R/W

W4

W2

W1

7 0 1 1 1 1 day Counter R/W D8

D4

D2

D1

8 1 0 0 0 10 day Counter R/W

D20

D10

9 1 0 0 1 1 month Counter R/W MO8 MO4 MO2 MO1

A 1 0 1 0 10 month Counter R/W

MO10 12/24 select Reg.

B 1 0 1 1 1 year Counter R/W Y8

Y4

Y2

Y1 Leap Year Reg.

R/W

W/O

R/O

R/W

AP/A

AH10

or AH20

12/24

LY1 LY0

LYE

W/O

TM2 TM1 TM0

C 1 1 0 0 10 year Counter R/W Y80 Y40 Y20 Y10 Timer Clock Select Reg. R/W TM3

R/O

TMFG

D 1 1 0 1 Control Reg. 1 W/O WTEN ALEN TMR BANK Control Reg. 1

W/O WTEN ALEN TMR BANK

E 1 1 1 0 Control Reg. 2

F 1 1 1 1 Control Reg. 3

R/O BSY

Control Reg. 2

R/W

CTFG ALFG XSTP

W/O TSTA TSTB WTRST

Control Reg. 3

R/O BSY

R/W

CTFG ALFG XSTP

W/O TSTA TSTB WTRST

*1) R/W bits can be read and written. R/O bits can only be read. W/O bits can only be written.

*2) It is no problem to attempt writing to R/O bits and blank bits, but the attempt will fail.

*3) If W/O bits and blank bits are read, the returned value is 0.

*4) The control registers 1, 2, and 3 have the same address assignment for BANK0 and BANK1.

6

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