CDP1878CE Просмотр технического описания (PDF) - Intersil

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CDP1878CE

CMOS Dual Counter-Timer

Intersil 

CDP1878C

MEMORY

CLOCK XTAL

ADDRESS

LINES

CLEAR

MWR

MRD

TPA

MAO

MA1

MA2

MA7

VSS

INT

CDP1802

TACL, TBCL

RESET

TPB/WR

RD

TPA

A0

A1

A2

CS

IO/MEM

INT

COUNTER - TIMER

DB0 - DB7

TAG

GATE

INPUTS

TBG

TAO

TAO

TIMER

OUTPUTS

TBO

TBO

DATA BUS

FIGURE 8. TYPICAL CDP1802 MEMORY-MAPPED SYSTEM

LATCH HIGH-ORDER

TPA

ADDRESS FOR CS

ADDRESS

HIGH BYTE

LOW BYTE

TPB/WR

DATA LATCHED

DATA FROM CPU

TO COUNTER-TIMER

VALID DATA

FIGURE 9. CDP1800-SERIES MEMORY-MAPPING WRITE CYCLE TIMING WAVEFORMS

TPA

ADDRESS

RD

HIGH BYTE

LOW BYTE

OUTPUT DRIVERS

ENABLED DISABLED

DATA FROM

COUNTER-TIMER

TO CPU

VALID DATA

FIGURE 10. CDP1800-SERIES MEMORY-MAPPING READ CYCLE TIMING WAVEFORMS

4-100

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