PI6C110EV Просмотр технического описания (PDF) - Pericom Semiconductor

Номер в каталоге

Компоненты Описание

Список матч

PI6C110EV

Clock Solution for 133 MHz Celeron/Pentium II/III Processors

Pericom Semiconductor 

PI6C110E

Clock Solution for 133 MHz

11223344556677889900112233445566778899001122334455667788990011221122334455667788990011223344556677889900112233445566778899001122112233445566778899001122334455667788990011223344556677889900C112211e22l33e44r5566o77n8899/00P1122e33n4455t66i77u8899m001122I33I44/55I66I7788I9900P11r2211o22c3344e55s66s7788o99r0011s22

Consider the command code and the byte count bytes required as the first two bytes of any transfer. The command code is software

programmable via the controller, but will be specified as 0000 0000 in the clock specification. The byte count byte is the number of

additional bytes required for the transfer, not counting the command code and byte count bytes. Additionally, the byte count byte is

required to be a minimum of 1 byte and a maximum of 32 bytes to satisfy the above requirement. For example:

Byte count byte

MSB

LSB

0000

0000

0000

0001

0000

0010

0000

0011

0000

0100

0000

0101

0000

0110

0000

0111

0010

0000

Notes

Not allowed. Must have at least one byte.

Data for functional and frequency select register (currently byte 0 in spec)

Reads first two bytes of data (byte 0, then byte 1)

Reads first three bytes of data (byte 0, 1, 2 in order)

Reads first four bytes of data (byte 0, 1, 2, 3 in order)

Reads first five bytes of data (byte 0, 1, 2, 3, 4 in order)

Reads first six bytes of data (byte 0, 1, 2, 3, 4, 5 in order)

Reads first seven bytes of data (byte 0, 1, 2, 3, 4, 5, 6 in order)

Max. byte count supported = 32

A transfer is considered valid after the acknowledge bit corresponding to the byte count is read by the controller. The serial controller

interface can be simplified by discarding the information in both the command code and the byte count bytes and simply reading all the

bytes that are sent to the clock driver after being addressed by the controller. It is expected that the controller will not provide more bytes

than the clock driver can handle.

7. Clock Stretching: The clock device must not hold/stretch the SCLK or SDATA lines low for more than 10 mS. Clock stretching is

discouraged and should only be used as a last resort. Stretching the clock/data lines for longer than this time puts the device in an error/

time-out mode and may not be supported in all platforms. It is assumed that all data transfers can be completed as specified without

the use of clock/data stretching.

8. General Call: It is assumed that the clock driver will not have to respond to the “general call.”

9. Electrical Characteristics: All electrical characteristics must meet the standard mode specifications found in section 15

of the I2C specification.

A) Pull-Up Resistors: There is a 100k internal resistor pull-ups on the SDATA and SCLK inputs. Assume that the board designer

will use a single external pull-up resistor for each line and that these values are in the 5-6K Ohm range. Assume one I2C device

per DIMM (serial presence detect), one I2C controller, one clock driver plus one/two more I2C devices on the platform for capacitive

loading purposes.

B) Input Glitch Filters: Only fast mode I2C devices require input glitch filters to suppress bus noise. The clock driver is specified

as a standard mode device and is not required to support this feature.

10. PWRDWN#: If a clock driver is placed in Power down mode, the SDATA and SCLK inputs are Tri-Stated and the device must retain

all programming information.

For specific I2C information consult the Philips I2C Peripherals Data Handbook ICI2 (1996)

13

PS8410

08/11/99

Share Link: