PI6C671FA Просмотр технического описания (PDF) - Pericom Semiconductor
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PI6C671FA Datasheet PDF : 7 Pages
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PI6C671F
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Power Management Functions
Any or all clocks can be enabled or shut down via the I2C control
interface. All clocks stop in the LOW state. CPU, SDRAM, and PCI
clocks wait for one rising edge of PCICLK_F followed by a falling
edge of the clock of interest before settling in the LOW state. To
reduce power consumption the PI6C671F clocks may be disabled in
accordance with the following table.
CPU_STOP# PCI_STOP# PWR_DWN#
X
X
0
0
0
1
0
1
1
1
0
1
1
1
1
CPUCLK,
SDRAM
LOW
LOW
LOW
66/60 MHz
66/60 MHz
PCICLK
LOW
LOW
33/30 MHz
LOW
33/30 MHz
Other
Clocks
LOW
Running
Running
Running
Running
Crystal &
VCOs
Off
Running
Running
Running
Running
2-Wire I2C Control
The I2C interface permits individual enable/disable of each
clock output and test mode enable.
The PI6C671F is a slave receiver device. It can not be read back.
Sub addressing is not supported. All preceding bytes must be sent
in order to change one of the control bytes.
Every bite put on the SDATA line must be 8-bits long (MSB first),
followed by an acknowledge bit generated by the receiving
device.
During normal data transfers SDATA changes only when SDCLK
is LOW. Exceptions: A HIGH to LOW transition on SDATA while
SDCLK is HIGH indicates a “start” condition. A LOW to HIGH
transition on SDATA while SDCLK is HIGH is a “stop” condition
and indicates the end of a data transfer cycle.
Each data transfer is initiated with a start condition and ended with
a stop condition. The first byte after a start condition is always a
7-bit address byte followed by a read/write bit. (HIGH = read from
addressed device, LOW= write to addressed device). If the device’s
own address is detected, PI6C671F generates an acknowledge by
pulling SDATA line LOW during ninth clock pulse, then accepts the
following data bytes until another start or stop condition is detected.
Following acknowledgement of the address byte (D2), two more
bytes must be sent:
1. “Command Code” byte, and
2. “Byte Count” byte.
Although the data bits on these two bytes are “don’t care,” they
must be sent and acknowledged.
The I2C interface is disabled when the PWR_DWN# pin is LOW.
Preset control register contents are retained.
I2C Serial Configuration
Byte 0: Functional and Frequency Select
Clock Register (1 = enable, 0 = disable)
Bit Pin No. @ Powerup
Description
7
0
(Reserved)
6
0
(Reserved, don't change)
5
0
(Reserved, don't change)
4
0
(Reserved, don't change)
3
23
1
48/24 MHz (Freq Select)
1 = 48 MHz, 0 =24 MHz
2
22
1
48/24 MHz (Freq Select)
1 = 48 MHz, 0 = 24 MHz
1
0
Bit1 Bit0
0
0
1 1 : Tri-State
1 0 : Spread Spectrum
0 1 : Test Mode
0 0 : Normal Operation
394
PS8137A 03/15/99
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