PCD3316 Просмотр технического описания (PDF) - Philips Electronics

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PCD3316

Caller-ID on Call Waiting (CIDCW) receiver

Philips Electronics 

Philips Semiconductors

PCD3316

CIDCW receiver

SDA

SCL

MASTER

U TRANSMITTER /

RECEIVER

SLAVE

RECEIVER

n Fig 9. I2C-bus configuration.

SLAVE

TRANSMITTER /

RECEIVER

MASTER

TRANSMITTER

MASTER

TRANSMITTER /

RECEIVER

MBA605

re7.12.2 START and STOP conditions

Both data and clock lines remain HIGH when the bus is not busy. A HIGH-to-LOW

stransition of the data line, while the clock is HIGH is defined as the START condition

t(S). A LOW-to-HIGH transition of the data line while the clock is HIGH is defined as a

rSTOP condition (P); see Figure 10.

icted SDA

SDA

SCL

SCL

S

P

START condition

STOP condition

MBA608

Fig 10. START and STOP conditions for the I2C-bus.

7.12.3 Bit transfer

One data bit is transferred during each clock pulse. The data on the SDA line must

remain stable during the HIGH period of the clock pulse as changes in the data line at

this time will be interpreted as a control signal; see Figure 11.

SDA

SCL

Fig 11. I2C-bus bit transfer.

data line

stable;

data valid

change

of data

allowed

MBA607

7.12.4 Acknowledge

The number of data bytes transferred between the START and the STOP conditions

from the transmitter to the receiver is unlimited. Each byte of eight bits is followed by

an acknowledge bit. The acknowledge bit is a HIGH level signal put on the bus by the

transmitter during which time the master generates an extra acknowledge-related

clock pulse.

A slave receiver which is addressed must generate an acknowledge after the

reception of each byte. Also a master receiver must generate an acknowledge after

the reception of each byte that has been clocked out of the slave transmitter.

9397 750 04824

Product specification

11 March 1999

© Philips Electronics N.V. 1999. All rights reserved.

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