TDC1016J5CX Просмотр технического описания (PDF) - Fairchild Semiconductor

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TDC1016J5CX

Video Speed D/A Converter

Fairchild Semiconductor 

TDC1016

PRODUCT SPECIFICATION

Functional Description

General Information

TTL/ECL buffers are used for all digital inputs to the

TDC1016. Logic family compatibility depends upon the

connection of power supplies. When single power supply

(-5.2V) operation is employed, all data, clock, and disable

inputs are compatible with differential ECL logic levels. All

digital inputs become compatible with TTL levels when dual

power supply (±5.0V) operation is used.

The internal 10-bit register latches data on the rising edge of

the clock (CLK) pulse. Currents from the current sources are

switched accordingly and combined in the resistor network

to give an analog output voltage. The magnitude of the out-

put voltage is directly proportional to the magnitude of the

digital input word.

The NFL and NFH inputs can be used to simplify system

calibration by forcing the analog output voltage to either its

zero-scale or full-scale value. The TDC1016 can be operated

in binary, inverse binary, two’s complement or inverse two’s

complement input data formats.

Power

The TDC1016 can be operated from a single -5.2V power

supply or from a dual ±5.0V power supply. For single power

supply operation, VCC is connected to DGND and all inputs

to the device become ECL compatible. When VCC is tied to

+5.0V, the inputs are TTL compatible.

The return path for the output from the 10 current sources is

AGND. The current return path for the digital section is

DGND. DGND and AGND should be returned to system

power supply ground by way of separate conductive paths to

prevent digital ground noise from disturbing the analog cir-

cuitry of the TDC1016. All AGND pins must be connected to

system analog ground.

Reference

The reference input is normally set to -1.0V with respect to

AGND. Adjusting this voltage is equivalent to adjusting sys-

tem gain The temperature stability of the TDC1016 analog

output (AOUT) depends primarily upon the temperature sta-

bility of the applied reference voltage

The internal operational amplifier of the TDC1016 is fre-

quency stabilized by an external 1 mF tantalum capacitor

connected between the COMP pin and VEE. A minimum of

1 mF is adequate for most applications, but 10 microfarads or

more is recommended for optimum performance. The nega-

tive side of this capacitor should be connected to VEE.

Controls

The NDIS inputs are used to disable the TDC1016 by

forcing its output to the zero-scale value (current sources

off). The NDIS inputs are asynchronous, active without

regard to the CLK inputs. The other digital control inputs are

synchronous, latched on the rising edge of the CLK pulse.

The rising edge of the CLK pulse transfers data from the

input lines to the internal 10-bit register. In TTL mode, the

inverted inputs for CLK, DATA, and NDIS are inactive and

should be left open.

The Input Coding Table illustrates the function of the digital

control inputs. A two’s complement mode is created by acti-

vating N2C with a Logic 0 When NFH and NFL are both

activated with a Logic 0 the input data to the 10-bit register is

inverted.

Data Inputs

Data inputs are ECL compatible when single power supply

operation is employed. The J5 and C2 packages allow for

differential ECL inputs while the J7 and B7 packages have

only single-ended inputs. When differential ECL data is

used, any data input can be inverted simply by reversing the

connections to the true and inverted data input pins. All

inverted input pins should be left open if single-ended ECL

or TTL modes are used. All data inputs have an internal

40 KW pullup resistor to VCC.

Analog Output

The analog output voltage is negative with respect to AGND

and varies proportionally with the magnitude of the input

data word. The output resistance at this point is 80W,

nominally.

No Connects

There are several pins labeled no connect (NC) on the

TDC1016 J5 and C2 packages, which have no connections

to the chip. These pins should be left open.

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