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TDA9852

I2C-bus controlled BTSC stereo/SAP decoder and audio processor

Philips Electronics 

Philips Semiconductors

I2C-bus controlled BTSC stereo/SAP

decoder and audio processor

Preliminary specification

TDA9852

LICENSE INFORMATION

A license is required for the use of this product. For further information, please contact

COMPANY

BRANCH

ADDRESS

THAT Corporation

Licensing Operations

Tokyo Office

734 Forest St.

Marlborough, MA 01752

USA

Tel.: (508) 229-2500

Fax: (508) 229-2590

405 Palm House, 1-20-2 Honmachi

Shibuya-ku, Tokyo 151

Japan

Tel.: (03) 3378-0915

Fax: (03) 3374-5191

QUICK REFERENCE DATA

SYMBOL

PARAMETER

CONDITIONS

MIN.

VCC

supply voltage

8.0

ICC

supply current

−

Vcomp(rms) input signal voltage (RMS value) 100% modulation L + R; fi = 300 Hz −

VoR,L(rms) output signal voltage (RMS value) 100% modulation L + R; fi = 300 Hz −

GLA

input level adjustment control

−3.5

αcs

stereo channel separation

fL = 300 Hz; fR = 3 kHz

25

THDL,R total harmonic distortion L + R

fi = 1 kHz

−

VI, O(rms) signal handling (RMS value)

THD < 0.5%

2

AVL

control range

−15

GC

volume control range

−71

LB

maximum loudness boost

fi = 40 Hz

−

S/N

signal-to-noise ratio

line out (mono); Vo = 0.5 V (RMS)

CCIR noise weighting filter

−

(peak value)

DIN noise weighting filter

−

(RMS value)

S/N

signal-to-noise ratio

audio section; Vo = 2 V (RMS);

gain = 0 dB

CCIR noise weighting filter

−

(peak value)

DIN noise weighting filter

−

(RMS value)

TYP.

8.5

75

250

500

−

35

0.2

−

−

−

17

60

73

94

107

MAX.

9.0

95

−

−

+4.0

−

−

−

+6

+16

−

−

−

−

−

UNIT

V

mA

mV

mV

dB

dB

%

V

dB

dB

dB

dB

dBA

dB

dBA

1997 Mar 11

3

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