CS7410-CQ Просмотр технического описания (PDF) - Cirrus Logic
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CS7410-CQ Datasheet PDF : 39 Pages
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CS7410
CD_BCK
CD_LRCK
DATA
0
C2P0
Invalid
Lower (Left Channel)
Left Channel
MSB
LSB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Upper (Left Channel)
Invalid
Lower (Right Channel)
Right Channel
MSB
LSB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Upper (Right Channel)
32-bit BCK, MSB First, Right Channel Low, C2P0 LSB First, Data latch timing high
CD_BCK
CD_LRCK
DATA
0
C2P0
Invalid
Upper (Right Channel)
Right Channel
MSB
LSB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Lower (Right Channel)
Invalid
Upper (Left Channel)
Left Channel
MSB
LSB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Lower (Left Channel)
32-bit BCK, MSB First, Left Channel Low, C2P0 MSB First, Data latch timing low
CD_BCK
CD_LRCK
DATA
0
C2P0
Invalid
Left Channel
MSB
LSB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Upper (Left Channel)
Lower (Left Channel)
Invalid
Right Channel
MSB
LSB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Upper (Right Channel)
Lower (Right Channel)
24-bit BCK, MSB First, Right Channel Low, C2P0 MSB First, Data latch timing high
Invalid
Left Channel
MSB
15 14 13 12 11 10 9 8 7 6 5
Upper (Left Channel)
CD_BCK
CD_LRCK
DATA
0
C2P0
Invalid
Left Channel
LSB
MSB
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Upper (Left Channel)
Lower (Left Channel)
Invalid
Right Channel
LSB
MSB
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Upper (Right Channel)
Lower (Right Channel)
24-bit BCK, LSB First, Right Channel Low, C2P0 MSB First, Data latch timing low
Invalid
Left Channel
LSB
0 1 2 3 4 5 6 7 8 9 10
Upper (Left Channel)
CD_BCK
CD_LRCK
DATA
0
Invalid
Left Channel
MSB
LSB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Invalid
Right Channel
MSB
LSB
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Invalid
24-bit BCK, MSB First, Right Channel Low, Data latch timing high (Note: no C2P0 for this format)
Left Channel
MSB
15 14 13 12 11 10 9 8 7 6 5
CD_BCK
CD_LRCK
DATA
C2P0
Right Channel
Left Channel
Right Channel
Left Channel
MSB
LSBMSB
LSBMSB
LSB MSB
LSBMSB
0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 15 14 13
Lower (Right Channel) Upper (Right Channel) Lower (Left Channel)
Upper (Left Channel)
Lower (Right Channel) Upper (Right Channel)
Lower (Left Channel)
Upper (Left Channel)
16-bit BCK, MSB First, Left Channel Low, C2P0 LSB First, Data latch timing high
Figure 14. CD Interface Timing Diagrams
DS553PP1
19
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