CXD3008Q Просмотр технического описания (PDF) - Sony Semiconductor

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CXD3008Q

CD Digital Signal Processor with Built-in Digital Servo

Sony Semiconductor 

CXD3008Q

Pin

No.

Symbol

I/O

68 EMPH O 1, 0

69 XTSL

70 DVSS2

71 XTAI

72 XTAO

73 SOUT

74 SOCK

75 XOLT

76 SQSO

77 SQCK

78 SCSY

79 SBSO

80 EXCK

I

——

I

O

O 1, 0

O 1, 0

O 1, 0

O 1, 0

I

I

O 1, 0

I

Description

Outputs a high signal when the playback disc has emphasis, and a low

signal when there is no emphasis.

Crystal selection input. Low when the crystal is 16.9344MHz; high when it is

33.8688MHz.

Digital GND.

Crystal oscillation circuit input. When the master clock is input externally,

input it from this pin.

Crystal oscillation circuit output.

Serial data output in servo block.

Serial data readout clock output in servo block.

Serial data latch output in servo block.

Sub-Q 80-bit, PCM peak or level data outputs. CD TEXT data output.

SQSO readout clock input.

GRSCOR resynchronization input.

Sub-Q P to W serial output.

SBSO readout clock input.

Notes)

• PCMD is a MSB first, two's complement output.

• GTOP is used to monitor the frame sync protection status. (High: sync protection window released.)

• XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before sync

protection.

• XPCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the EFM signal

transition point coincide.

• The GFS signal goes high when the frame sync and the insertion protection timing match.

• RFCK is derived from the crystal accuracy, and has a cycle of 136µs. (during normal speed)

• C2PO represents the data error status.

• XROF is generated when the 32K RAM exceeds the ±28F jitter margin.

Combination of Monitor Pin Outputs

Command bit

MTSL1 MTSL0

0

0

0

1

1

0

XUGF

MNT0

RFCK

Output data

XPCK

MNT1

XPCK

GFS

MNT2

XROF

C2PO

MNT3

GTOP

–6–

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