XRD98L59AIG Просмотр технического описания (PDF) - Exar Corporation

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XRD98L59AIG

CCD Image Digitizers with CDS, PGA and 10-Bit A/D

Exar Corporation 

XRD98L59

SDI

SCLK

LOAD

LSB

MSB

Data Bits

Address Bits

D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 A3

data input

Register Array

register

select

Address

Decoder

Figure 4. Serial Interface Timing Diagram

Reg. Name

Gain

Target Offset

Delay

Clock

Control

Calibration

FDAC (msb)

FDAC (lsb)

CDAC

•

•

•

Reset

Address bits

A3 A2 A1 A0

0 0 00

0 0 01

0 0 10

0 0 11

0 1 00

0 1 01

0 1 10

0 1 11

1 0 00

Data bits

D7 D6

D5

D4

D3

D2

D1

D0

Gain

[7:0]

Offset [5:0]

SBLK delay [2:0]

SPIX delay[2:0]

Exar test

RST rej Exar test Clamp opt SBLK pol SPIXpol Clamp pol CAL pol

Delay test ADCIN PD

OE

Cal Hold Speed Up DNS 1 DNS 0

Man

DAC

FDAC

[9:2]

FDAC [1:0]

CDAC [3:0]

Not Used

1 1 11

Reset

Table 1. Serial Interface Register Address Map

Rev. 2.00

9

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