Preliminary W91030B
Nth byte data
(N + 1)th byte data
Demodulated
stop start
stop start
internal b6 b7
1
0 b0 b1 b2 b3 b4 b5 b6 b7
1
0 b0
bit stream
t RL
FDRN
DCLK
Note 1
t DDS
t DDH
Note 2
1/f DCLK1
DATA
b5 b6 b7 b0 b1 b2 b3 b4 b5 b6 b7
b0
(N - 1)th byte data
Nth byte data
Notes:
1. FDRN cleared to high by DCLK.
2. FDRN not cleared, low for maximum time (1/2 bit width).
Figure 8-8. Serial Data Interface Timing of FSK Demodulation in Mode 1
- 20 -