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CDP1852 Просмотр технического описания (PDF) - Intersil

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CDP1852 Datasheet PDF : 9 Pages
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CDP1852, CDP1852C
Application Information
In a CDP1800 series microprocessor-based system where
MRD is used to distinguish between INP and OUT
instructions, an lNP instruction is assumed to occur at the
beginning of every I/O cycle because MRD starts high.
Therefore, at the start of an OUT instruction, which uses the
same 3-bit N code as that used for selection of an input port,
the input device is selected for a short time (see Figure 8).
This condition forces SR low and sets the internal SR latch
(see Figure 3). In a small system with unique N codes for
inputs and outputs, this situation does not arise. Using the
CDP1853 N-bit decoder or equivalent logic to decode the N
lines after TPA prevents dual selection in larger systems
(see Figure 9 and Figure 10).
MRD
N0
N1
N2
SELECT
6D
65
SR
FIGURE 8. EXECUTION OF A “65” OUTPUT INSTRUCTION SHOWING MOMENTARY SELECTION OF INPUT PORT “D”
2
N0
N1 3
14
N2
1 OF 8
DECODER
EN
4
5 OUT 0
OUT 1
6 OUT 2
7 OUT 3
12 OUT 4
11 OUT 5
10 OUT 6
9
OUT 7
TPA
TPB
CE
EN
(NOTE 1)
OUTPUT
FIGURE 9. CDP1853 TIMING WAVEFORMS
NOTE:
1. Output enabled when EN = HIGH. Internal signal shown for ref-
erence only (See Figure 1).
13
CE
CLOCK A 1
Qn
(TPA)
CLOCK B 15
(TPB)
FIGURE10. CDP1853 FUNCTIONAL DIAGRAM
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