STK12C68-C45I Просмотр технического описания (PDF) - Simtek Corporation
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STK12C68-C45I Datasheet PDF : 20 Pages
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STK12C68 (SMD5962-94599)
Packages
VCAP 1
A12 2
A7 3
A6 4
A5 5
A4 6
A3 7
A2 8
A1 9
A0 10
DQ0 11
DQ1 12
DQ2 13
VSS 14
28 VCCX
27 W
26 HSB
25 A8
24 A9
23 A11
22 G
21 A10
20 E
19 DQ7
18 DQ6
17 DQ5
16 DQ4
15 DQ3
28-pin SOIC
28-pin DIP
28-pin LCC
Pin Descriptions
Pin Name
A12-A0
DQ7-DQ0
E
W
G
VCCX
HSB
I/O
Input
I/O
Input
Input
Input
Power Supply
I/O
VCAP
VSS
Power Supply
Power Supply
Description
Address: The 13 address inputs select one of 8,192 bytes in the nvSRAM array
Data: Bi-directional 8-bit data bus for accessing the nvSRAM
Chip Enable: The active low E input selects the device
Write Enable: The active low W enables data on the DQ pins to be written to the address
location latched by the falling edge of E
Output Enable: The active low G input enables the data output buffers during read cycles.
De-asserting G high caused the DQ pins to tri-state.
Power: 5.0V, +10%, -10%
Hardware Store Busy: When low this output indicates a Store is in progress. When pulled
low external to the chip, it will initiate a nonvolatile STORE operation. A weak pull up resistor
keeps this pin high if not connected. (Connection Optional).
AutoStore Capacitor: Supplies power to nvSRAM during power loss to store data from
SRAM to nonvolatile storage elements.
Ground
Document Control #ML0008 Rev 0.7
2
February 2007
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